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Phiroze N. Parakh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown
    CGaAs PowerPC FXU. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:730-735 [Conf]
  2. Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah
    Congestion Driven Quadratic Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:275-278 [Conf]
  3. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:95-103 [Conf]
  4. Phiroze N. Parakh, Richard B. Brown
    Crosstalk constrained global route embedding. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:201-206 [Conf]
  5. Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis
    Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:53-59 [Conf]
  6. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:472-487 [Journal]
  7. Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge
    Overview of complementary GaAs technology for high-speed VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:47-51 [Journal]

  8. A robust approach to lithography friendly design implementation. [Citation Graph (, )][DBLP]


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