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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2003 (conf/slip/2003)

  1. Victor N. Kravets, Prabhakar Kudva
    Understanding metrics in logic synthesis for routability enhancement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:3-5 [Conf]
  2. Ketan N. Patel, Igor L. Markov
    Error-correction and crosstalk avoidance in DSM busses. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:9-14 [Conf]
  3. Jason Helge Anderson, Farid N. Najm
    Switching activity analysis and pre-layout activity prediction for FPGAs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:15-21 [Conf]
  4. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Sequential delay budgeting with interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:23-30 [Conf]
  5. Joachim Pistorius, Mike Hutton
    Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:31-38 [Conf]
  6. Martijn T. Bennebroek
    Validation of wire length distribution models on commercial designs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:41- [Conf]
  7. Joni Dambre, Dirk Stroobandt, Jan Van Campenhout
    Fast estimation of the partitioning rent characteristic using a recursive partitioning model. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:45-52 [Conf]
  8. Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis
    Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:53-59 [Conf]
  9. Andrew B. Kahng, Xu Xu
    Accurate pseudo-constructive wirelength and congestion estimation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:61-68 [Conf]
  10. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang
    Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:71-76 [Conf]
  11. Shankar Balachandran, Dinesh Bhatia
    A-priori wirelength and interconnect estimation based on circuit characteristics. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:77-84 [Conf]
  12. Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright
    Prediction of interconnect pattern density distribution: derivation, validation, and applications. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:85-91 [Conf]
  13. Eli Chiprout
    Early electrical wire projections and implications. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:95- [Conf]
  14. Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska
    Wire length prediction in constraint driven placement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:99-105 [Conf]
  15. Pranav Anbalagan, Jeffrey A. Davis
    Maximum multiplicity distributions (MMD). [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:107-113 [Conf]
  16. Jian Liu, Meigen Shen, Li-Rong Zheng, Hannu Tenhunen
    System level interconnect design for network-on-chip using interconnect IPs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:117-124 [Conf]
  17. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
    Global interconnect trade-off for technology over memory modules to application level: case study. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:125-132 [Conf]
  18. Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham
    A hierarchical three-way interconnect architecture for hexagonal processors. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:133-139 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002