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Karem A. Sakallah: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi
    Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:32-46 [Conf]
  2. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    ShatterPB: symmetry-breaking for pseudo-Boolean formulas. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:883-886 [Conf]
  3. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Dynamic symmetry-breaking for improved Boolean optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:445-450 [Conf]
  4. Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah
    Refinement strategies for verification methods based on datapath abstraction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:19-24 [Conf]
  5. Maher N. Mneimneh, Karem A. Sakallah, John Moondanos
    Preserving synchronizing sequences of sequential circuits after retiming. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:579-584 [Conf]
  6. João P. Marques Silva, Karem A. Sakallah
    Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation. [Citation Graph (0, 0)][DBLP]
    CAV, 2000, pp:3- [Conf]
  7. Hossein M. Sheini, Bart Peintner, Karem A. Sakallah, Martha E. Pollack
    On Solving Soft Temporal Constraints Using SAT Techniques. [Citation Graph (0, 0)][DBLP]
    CP, 2005, pp:607-621 [Conf]
  8. Hossein M. Sheini, Karem A. Sakallah
    A SAT-Based Decision Procedure for Mixed Logical/Integer Linear Problems. [Citation Graph (0, 0)][DBLP]
    CPAIOR, 2005, pp:320-335 [Conf]
  9. Zaher S. Andraus, Karem A. Sakallah
    Automatic abstraction and verification of verilog models. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:218-223 [Conf]
  10. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Shatter: efficient symmetry-breaking for boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:836-839 [Conf]
  11. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Solving difficult SAT instances in the presence of symmetry. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:731-736 [Conf]
  12. Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah
    Satometer: how much have we searched? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:737-742 [Conf]
  13. Ajay Chandna, C. David Kibler, Richard B. Brown, Mark Roberts, Karem A. Sakallah
    The Aurora RAM Compiler. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:261-266 [Conf]
  14. V. Chandramouli, Karem A. Sakallah
    Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:617-622 [Conf]
  15. Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov
    Exploiting structure in symmetry detection for CNF. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:530-534 [Conf]
  16. Victor N. Kravets, Karem A. Sakallah
    M32: A Constructive multilevel Logic Synthesis System. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:336-341 [Conf]
  17. Maher N. Mneimneh, Fadi A. Aloul, Chris Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin
    Scalable Hybrid Verification of Complex Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:41-46 [Conf]
  18. Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov
    AMUSE: a minimally-unsatisfiable subformula extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:518-523 [Conf]
  19. Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah
    Congestion Driven Quadratic Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:275-278 [Conf]
  20. Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun
    Analysis and Design of Latch-Controlled Synchronous Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:111-117 [Conf]
  21. João P. Marques Silva, Karem A. Sakallah
    Boolean satisfiability in electronic design automation. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:675-680 [Conf]
  22. João P. Marques Silva, Karem A. Sakallah
    Dynamic Search-Space Pruning Techniques in Path Sensitization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:705-711 [Conf]
  23. Jesse Whittemore, Joonyoung Kim, Karem A. Sakallah
    SATIRE: A New Incremental Satisfiability Engine. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:542-545 [Conf]
  24. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah
    Functional Timing Analysis for IP Characterization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:731-736 [Conf]
  25. Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    An Advanced Timing Characterization Method Using Mode Dependency. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:657-660 [Conf]
  26. Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah
    Search-Based SAT Using Zero-Suppressed BDDs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1082- [Conf]
  27. V. Chandramouli, Jesse Whittemore, Karem A. Sakallah
    AFTA: A Formal Delay Model for Functional Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:350-355 [Conf]
  28. Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva
    On Applying Incremental Satisfiability to Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:380-384 [Conf]
  29. Victor N. Kravets, Karem A. Sakallah
    Constructive Library-Aware Synthesis Using Symmetries. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:208-0 [Conf]
  30. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A boolean satisfiability-based incremental rerouting approach with application to FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:560-565 [Conf]
  31. Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Breaking Instance-Independent Symmetries in Exact Graph Coloring. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:324-331 [Conf]
  32. Karem A. Sakallah, Fadi A. Aloul, João P. Marques Silva
    An Experimental Study of Satisfiability Search Heuristics. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:745- [Conf]
  33. Hossein M. Sheini, Karem A. Sakallah
    Pueblo: A Modern Pseudo-Boolean SAT Solver. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:684-685 [Conf]
  34. Hossein M. Sheini, Karem A. Sakallah
    Ario: A Linear Integer Arithmetic Logic Solver. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:47-48 [Conf]
  35. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:167-175 [Conf]
  36. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:360-369 [Conf]
  37. João P. Marques Silva, Karem A. Sakallah
    Robust Search Algorithms for Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    FTCS, 1997, pp:152-161 [Conf]
  38. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    FORCE: a fast and easy-to-implement variable-ordering heuristic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:116-119 [Conf]
  39. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Faster SAT and Smaller BDDs via Common Function Structure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:443-448 [Conf]
  40. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Generic ILP versus specialized 0-1 ILP: an update. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:450-457 [Conf]
  41. Timothy M. Burks, Karem A. Sakallah
    Min-max linear programming and the timing analysis of digital circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:152-155 [Conf]
  42. Timothy M. Burks, Karem A. Sakallah
    Optimization of critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:468-473 [Conf]
  43. Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge
    Identification of critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:137-141 [Conf]
  44. David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah
    Timing verification of sequential domino circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:127-132 [Conf]
  45. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
    Using constraint geometry to determine maximum rate pipeline clocking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:142-148 [Conf]
  46. Victor N. Kravets, Karem A. Sakallah
    Generalized Symmetries in Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:526-532 [Conf]
  47. Victor N. Kravets, Karem A. Sakallah
    Resynthesis of multi-level circuits under tight constraints using symbolic optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:687-693 [Conf]
  48. Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun
    check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:552-555 [Conf]
  49. Emily J. Shriver, Karem A. Sakallah
    Ravel: assigned-delay compiled-code logic simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:364-368 [Conf]
  50. João P. Marques Silva, Karem A. Sakallah
    GRASP - a new search algorithm for satisfiability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:220-227 [Conf]
  51. João P. Marques Silva, Karem A. Sakallah, Luís M. Vidigal
    FPD - An Environment for Exact Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:212-215 [Conf]
  52. Hakan Yalcin, John P. Hayes, Karem A. Sakallah
    An approximate timing analysis method for datapath circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:114-118 [Conf]
  53. Hossein M. Sheini, Karem A. Sakallah
    SMT(CLU): a step toward scalability in system verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:844-851 [Conf]
  54. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:64-69 [Conf]
  55. Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah
    On Solving Stack-Based Incremental Satisfiability Problems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:379-382 [Conf]
  56. Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown
    Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:361-364 [Conf]
  57. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
    Optimal Clocking of Circular Pipelines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:642-650 [Conf]
  58. João P. Marques Silva, Karem A. Sakallah
    An Analysis of Path Sensitization Criteria. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:68-72 [Conf]
  59. Somanathan C. Menon, Karem A. Sakallah
    Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and On-section Clock Derivation. [Citation Graph (0, 0)][DBLP]
    ICSI, 1990, pp:550-558 [Conf]
  60. João P. Marques Silva, Karem A. Sakallah
    Conflict Analysis in Search Algorithms for Satisfiability. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1996, pp:467-469 [Conf]
  61. Joonyoung Kim, João P. Marques Silva, Karem A. Sakallah
    Satisfiability-Based Functional Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:362-372 [Conf]
  62. Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov
    Efficient Symmetry Breaking for Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    IJCAI, 2003, pp:271-276 [Conf]
  63. Mark H. Liffiton, Michael D. Moffitt, Martha E. Pollack, Karem A. Sakallah
    Identifying Conflicts in Overconstrained Temporal Problems. [Citation Graph (0, 0)][DBLP]
    IJCAI, 2005, pp:205-211 [Conf]
  64. Ayman I. Kayssi, Karem A. Sakallah
    Macromodel Simplification Using Dimensional Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:335-338 [Conf]
  65. João P. Marques Silva, Karem A. Sakallah
    Efficient and Robust Test Generation-Based Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:303-306 [Conf]
  66. Michael A. Riepe, Karem A. Sakallah
    Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:74-81 [Conf]
  67. Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
    A comparative study of two Boolean formulations of FPGA detailed routing constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:222-227 [Conf]
  68. Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
    sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:182-187 [Conf]
  69. Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah
    ZBDD-Based Backtrack Search SAT Solver. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:131-136 [Conf]
  70. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:137-142 [Conf]
  71. Leyla Nazhandali, Karem A. Sakallah
    Majority-Based Decomposition of Carry Logic in Binary Adders. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:179-184 [Conf]
  72. Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw
    Robust SAT-Based Search Algorithm for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:167-177 [Conf]
  73. Maher N. Mneimneh, Karem A. Sakallah
    Computing Vertex Eccentricity in Exponentially Large Graphs: QBF Formulation and Solution. [Citation Graph (0, 0)][DBLP]
    SAT, 2003, pp:411-425 [Conf]
  74. Mark H. Liffiton, Karem A. Sakallah
    On Finding All Minimally Unsatisfiable Subformulas. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:173-186 [Conf]
  75. Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João P. Marques Silva, Karem A. Sakallah
    A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:467-474 [Conf]
  76. Hossein M. Sheini, Karem A. Sakallah
    A Scalable Method for Solving Satisfiability of Integer Linear Arithmetic Logic. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:241-256 [Conf]
  77. Hossein M. Sheini, Karem A. Sakallah
    From Propositional Satisfiability to Satisfiability Modulo Theories. [Citation Graph (0, 0)][DBLP]
    SAT, 2006, pp:1-9 [Conf]
  78. Hossein M. Sheini, Karem A. Sakallah
    A Progressive Simplifier for Satisfiability Modulo Theories. [Citation Graph (0, 0)][DBLP]
    SAT, 2006, pp:184-197 [Conf]
  79. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Satisfiability-Based Detailed FPGA Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:574-577 [Conf]
  80. Trevor N. Mudge, Richard B. Brown, William P. Bimingham, Jeffrey A. Dykstra, Ayman I. Kayssi, Ronald J. Lomax, Kunle Olukotun, Karem A. Sakallah, Raymond A. Milano
    The Design of a Microsupercomputer. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:57-64 [Journal]
  81. Maher N. Mneimneh, Karem A. Sakallah
    Principles of Sequential-Equivalence Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:248-257 [Journal]
  82. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2004, v:10, n:12, pp:1562-1596 [Journal]
  83. Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov
    Efficient Symmetry Breaking for Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:5, pp:549-558 [Journal]
  84. João P. Marques Silva, Karem A. Sakallah
    GRAPS: A Search Algorithm for Propositional Satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:5, pp:506-521 [Journal]
  85. Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
    A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:688-696 [Journal]
  86. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Solving difficult instances of Boolean satisfiability in the presence of symmetry. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1117-1137 [Journal]
  87. Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah
    Satometer: how much have we searched? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:995-1004 [Journal]
  88. David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah
    Timing verification of sequential dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:645-658 [Journal]
  89. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
    Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1526-1545 [Journal]
  90. Ayman I. Kayssi, Karem A. Sakallah
    Timing models for gallium arsenide direct-coupled FET logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:384-393 [Journal]
  91. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A new FPGA detailed routing approach via search-based Booleansatisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:674-684 [Journal]
  92. Karem A. Sakallah, Yao-Tsung Yen, Steve S. Greenberg
    A first-order charge conserving MOS capacitance model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:1, pp:99-108 [Journal]
  93. Karem A. Sakallah, Stephen W. Director
    SAMSON2: An Event Driven VLSI Circuit Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:4, pp:668-684 [Journal]
  94. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
    Synchronization of pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1132-1146 [Journal]
  95. Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun
    Analysis and design of latch-controlled synchronous digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:322-333 [Journal]
  96. Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
    sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:814-820 [Journal]
  97. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    Fast and accurate timing characterization using functionalinformation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:315-331 [Journal]
  98. Luís Guerra e Silva, João P. Marques Silva, Luis Miguel Silveira, Karem A. Sakallah
    Satisfiability models and algorithms for circuit delay computation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:137-158 [Journal]
  99. Michael A. Riepe, Karem A. Sakallah
    Transistor placement for noncomplementary digital VLSI cell synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:81-107 [Journal]
  100. Michael A. Riepe, Karem A. Sakallah
    The edge-based design rule model revisited. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:463-486 [Journal]
  101. Arathi Ramani, Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul
    Breaking Instance-Independent Symmetries In Exact Graph Coloring. [Citation Graph (0, 0)][DBLP]
    J. Artif. Intell. Res. (JAIR), 2006, v:26, n:, pp:289-322 [Journal]
  102. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
    Symmetry breaking for pseudo-Boolean formulas. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2007, v:12, n:, pp:- [Journal]
  103. Fadi A. Aloul, Arathi Ramani, Karem A. Sakallah, Igor L. Markov
    Solution and Optimization of Systems of Pseudo-Boolean Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1415-1424 [Journal]
  104. Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge
    Critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:273-291 [Journal]
  105. Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown
    Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:113-129 [Journal]
  106. Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge
    Overview of complementary GaAs technology for high-speed VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:47-51 [Journal]

  107. Faster symmetry discovery using sparsity of symmetries. [Citation Graph (, )][DBLP]


  108. Improved Design Debugging Using Maximum Satisfiability. [Citation Graph (, )][DBLP]


  109. Reveal: A Formal Verification Tool for Verilog Designs. [Citation Graph (, )][DBLP]


  110. Searching for Autarkies to Trim Unsatisfiable Clause Sets. [Citation Graph (, )][DBLP]


  111. Generalizing Core-Guided Max-SAT. [Citation Graph (, )][DBLP]


  112. Symmetry and Satisfiability: An Update. [Citation Graph (, )][DBLP]


  113. Dynamic symmetry-breaking for Boolean satisfiability. [Citation Graph (, )][DBLP]


  114. A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas. [Citation Graph (, )][DBLP]


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