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Paul Villarrubia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A Practical Methodology for Early Buffer and Wire Resource Allocation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:189-194 [Conf]
  2. Stephen D. Posluszny, N. Aoki, D. Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
    "Timing closure by design, " a high frequency microprocessor design methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:712-717 [Conf]
  3. Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
    Diffusion-based placement migration. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:515-520 [Conf]
  4. Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
    Transformational Placement and Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:194-201 [Conf]
  5. Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
    On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:311-319 [Conf]
  6. Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
    Free space management for cut-based placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:746-751 [Conf]
  7. Haoxing Ren, David Zhigang Pan, Paul Villarrubia
    True crosstalk aware incremental placement with noise map. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:402-409 [Conf]
  8. Shervin Hojat, Paul Villarrubia
    An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:206-210 [Conf]
  9. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:95-103 [Conf]
  10. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  11. Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
    A semi-persistent clustering technique for VLSI circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:200-207 [Conf]
  12. Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
    The ISPD2005 placement contest and benchmark suite. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:216-220 [Conf]
  13. Paul Villarrubia
    Important placement considerations for modern VLSI chips. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:6- [Conf]
  14. Paul Villarrubia
    Physical design tools for hierarchy. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:184- [Conf]
  15. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:472-487 [Journal]
  16. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A practical methodology for early buffer and wire resource allocation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:573-583 [Journal]
  17. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
    A Fast Hierarchical Quadratic Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:678-691 [Journal]
  18. Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris Chu
    RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:453-458 [Conf]

  19. Fast Electrical Correction Using Resizing and Buffering. [Citation Graph (, )][DBLP]


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