The SCEAS System
Navigation Menu

Search the dblp DataBase


Subodh M. Reddy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan
    Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:414-419 [Conf]
  2. Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori
    Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:610-615 [Conf]
  3. Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
    Analyzing timing uncertainty in mesh-based clock architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1097-1102 [Conf]
  4. Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai
    A sliding window scheme for accurate clock mesh analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:939-946 [Conf]
  5. Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai
    Clock Distribution Architectures: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:85-91 [Conf]
  6. Subodh M. Reddy, Rajeev Murgai
    Accurate Substrate Noise Analysis Based on Library Module Characterization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:355-362 [Conf]

Search in 0.026secs, Finished in 0.027secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002