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Hongyu Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hongyu Chen, Chung-Kuan Cheng
    A multi-level transmission line network approach for multi-giga hertz clock distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:103-106 [Conf]
  2. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang
    Optimal planning for mesh-based power distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:444-449 [Conf]
  3. Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng
    A multiple level network approach for clock skew minimization with process variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:263-268 [Conf]
  4. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton
    Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:73-78 [Conf]
  5. Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
    An algebraic multigrid solver for analytical placement with layout based clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:794-799 [Conf]
  6. Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng
    Communication latency aware low power NoC synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:574-579 [Conf]
  7. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
    The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:13-20 [Conf]
  8. Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai
    A sliding window scheme for accurate clock mesh analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:939-946 [Conf]
  9. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
    Improving the efficiency of static timing analysis with false paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:527-531 [Conf]
  10. Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris
    Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:497-502 [Conf]
  11. Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
    Physical Planning Of On-Chip Interconnect Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:30-35 [Conf]
  12. Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng
    Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:111-118 [Conf]
  13. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
    Unified quadratic programming approach for mixed mode placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:193-199 [Conf]
  14. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
    Revisiting floorplan representations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:138-143 [Conf]
  15. Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai
    Clock Distribution Architectures: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:85-91 [Conf]
  16. Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
    Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:251-256 [Conf]
  17. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang
    Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:71-76 [Conf]
  18. Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng
    Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:85-89 [Conf]
  19. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
    The Y architecture for on-chip interconnect: analysis and methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:588-599 [Journal]
  20. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
    Floorplan representations: Complexity and connections. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:55-80 [Journal]

  21. Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. [Citation Graph (, )][DBLP]


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