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Publications of Author

1. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
   A Structured System Methodology for FPGA Based System-on-A-Chip Design. [Citation Graph (0, 0)][DBLP]
   FCCM, 2004, pp:271-272 [Conf]
   
2. N. Pete Sedcole, Peter Y. K. Cheung
   Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. [Citation Graph (0, 0)][DBLP]
   FPGA, 2007, pp:178-187 [Conf]
   
3. N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght
   Modular Partial Reconfiguration in Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:211-216 [Conf]
   
4. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
   A Reconfigurable Platform for Real-Time Embedded Video Image Processing. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:606-615 [Conf]
   
5. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
   A Structured Methodology for System-on-an-FPGA Design. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1047-1051 [Conf]
   
6. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
   On-FPGA Communication Architectures and Design Factors. [Citation Graph (0, 0)][DBLP]
   FPL, 2006, pp:1-8 [Conf]
   
7. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
   On-Chip Communication in Run-Time Assembled Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
   ICSAMOS, 2006, pp:168-176 [Conf]
   
8. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam
   A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. [Citation Graph (0, 0)][DBLP]
   NOCS, 2007, pp:173-182 [Conf]
   
9. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
   Run-Time Integration of Reconfigurable Video Processing Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1003-1016 [Journal]
   
10. 
    Measuring and modeling FPGA clock variability. [Citation Graph (, )][DBLP]
    
    
11. 
    High-throughput interconnect wave-pipelining for global communication in FPGAs. [Citation Graph (, )][DBLP]
    
    
12. 
    Degradation in FPGAs: measurement and modelling. [Citation Graph (, )][DBLP]
    
    
13. 
    Combating process variation on FPGAS with a precise at-speed delay measurement method. [Citation Graph (, )][DBLP]
    
    
14. 
    Fault tolerant methods for reliability in FPGAs. [Citation Graph (, )][DBLP]
    
    
15. 
    Compensating for variability in FPGAs by re-mapping and re-placement. [Citation Graph (, )][DBLP]
    
    
16. 
    Characterisation of FPGA Clock Variability. [Citation Graph (, )][DBLP]
    
    
17. 
    Interconnection lengths and delays estimation for communication links in FPGAs. [Citation Graph (, )][DBLP]
    
    
18. 
    Global interconnections in FPGAs: modeling and performance analysis. [Citation Graph (, )][DBLP]
    
    
19. 
    Implementation of Wave-Pipelined Interconnects in FPGAs. [Citation Graph (, )][DBLP]