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Rainer G. Spallek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jens Braunes, Steffen Köhler, Annett Königsmann, Rainer G. Spallek
    Ein Zwischenformat-Profiler für das RECAST-Framework. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:33-38 [Conf]
  2. Jens Braunes, Steffen Köhler, Rainer G. Spallek
    RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2004, pp:156-166 [Conf]
  3. Steffen Köhler, Martin Zimmerling, Martin Zabel, Rainer G. Spallek
    Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:142-151 [Conf]
  4. Gert Markwardt, Günter Kemnitz, Rainer G. Spallek
    A RISC Processor with Extended Forwarding. [Citation Graph (0, 0)][DBLP]
    ARCS, 1997, pp:163-169 [Conf]
  5. Thomas B. Preuber, Rainer G. Spallek
    Analysis of a Fully-Scalable Digital Fractional Clock Divider. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:173-177 [Conf]
  6. Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube
    Formal Verification for Microprocessors with Extendable Instruction Set. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:47-55 [Conf]
  7. Thomas Preußer, Steffen Köhler, Rainer G. Spallek
    RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:130-135 [Conf]
  8. Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz
    A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1164-1167 [Conf]
  9. Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek
    Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:781-790 [Conf]
  10. Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube
    Formal Verification of a Reconfigurable Microprocessor. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:781-784 [Conf]
  11. Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
    Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:411-415 [Conf]
  12. Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek
    Prototyping Framework for Reconfigurable Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:6-16 [Conf]
  13. Sergej Sawitzki, Rainer G. Spallek
    Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1119-1122 [Conf]
  14. Sergej Sawitzki, Rainer G. Spallek
    A Concept for an Evaluation Framework for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:475-480 [Conf]
  15. Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek
    Improving Code Efficiency for Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  16. Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
    Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:706-708 [Conf]
  17. Raimar Falke, Michael Peter, Achim Gratz, Rainer G. Spallek
    Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten Umgebungen. [Citation Graph (0, 0)][DBLP]
    Java-Informations-Tage, 1998, pp:354-363 [Conf]
  18. Achim Gratz, Rainer G. Spallek
    Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen Plattformen. [Citation Graph (0, 0)][DBLP]
    MMB (Kurzbeiträge), 1997, pp:51-58 [Conf]
  19. Jens Braunes, Rainer G. Spallek
    A Compiler-Oriented Architecture Description for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:443-448 [Conf]

  20. Implementation of Architecture Concepts for Hardware Agent Systems. [Citation Graph (, )][DBLP]


  21. An Embedded GC Module with Support for Multiple Mutators and Weak References. [Citation Graph (, )][DBLP]


  22. Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor. [Citation Graph (, )][DBLP]


  23. Generating the trace qualification configuration for MCDS from a high level language. [Citation Graph (, )][DBLP]


  24. Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. [Citation Graph (, )][DBLP]


  25. Mapping basic prefix computations to fast carry-chain structures. [Citation Graph (, )][DBLP]


  26. Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. [Citation Graph (, )][DBLP]


  27. Enabling constant-time interface method dispatch in embedded Java processors. [Citation Graph (, )][DBLP]


  28. Bump-pointer method caching for embedded Java processors. [Citation Graph (, )][DBLP]


  29. Application requirements and efficiency of embedded Java bytecode multi-cores. [Citation Graph (, )][DBLP]


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