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Heiko Hinkelmann:
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- Heiko Hinkelmann, Peter Zipf, Manfred Glesner
A metric for the energy-efficiency of dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP] ARCS Workshops, 2006, pp:152-161 [Conf]
- Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner
Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. [Citation Graph (0, 0)][DBLP] ARCS Workshops, 2005, pp:45-51 [Conf]
- Hua Zhong, Leandro Soares Indrusiak, Heiko Hinkelmann, Manfred Glesner
Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2006, pp:160-167 [Conf]
- Heiko Hinkelmann, Peter Zipf, Manfred Glesner
A Concept for a Profile-based Dynamic Reconfiguration Mechanism. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2006, pp:105-110 [Conf]
- Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. [Citation Graph (0, 0)][DBLP] SAMOS, 2005, pp:12-21 [Conf]
- Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner
A switch architecture and signal synchronization for GALS system-on-chips. [Citation Graph (0, 0)][DBLP] SBCCI, 2004, pp:210-215 [Conf]
- Heiko Hinkelmann, Peter Zipf, Manfred Glesner
Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. [Citation Graph (0, 0)][DBLP] AHS, 2006, pp:436-441 [Conf]
- Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner
Multitasking Support for Dynamically Reconfig Urable Systems. [Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-6 [Conf]
- Heiko Hinkelmann, Tudor Murgan, G. Liu, Peter Zipf, Manfred Glesner
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2007, pp:185-191 [Conf]
- Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, P. B. Bacinschi, Manfred Glesner
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2007, pp:7-14 [Conf]
- Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner
A Customizable LEON2-Based VLIW Processor. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2007, pp:55-60 [Conf]
- Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). [Citation Graph (0, 0)][DBLP] it - Information Technology, 2007, v:49, n:3, pp:174-0 [Journal]
A Power Estimation Model for an FPGA-based Softcore Processor. [Citation Graph (, )][DBLP]
Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]
Application-specific reconfigurable processors. [Citation Graph (, )][DBLP]
An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. [Citation Graph (, )][DBLP]
Towards a unique FPGA-based identification circuit using process variations. [Citation Graph (, )][DBLP]
Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. [Citation Graph (, )][DBLP]
TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor. [Citation Graph (, )][DBLP]
A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support. [Citation Graph (, )][DBLP]
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