The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Thilo Pionteck: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner
    Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:45-51 [Conf]
  2. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Lukusa D. Kabulepa, Manfred Glesner
    Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:155-164 [Conf]
  3. Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
    Reconfigurable platforms for ubiquitous computing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:377-389 [Conf]
  4. Thilo Pionteck, Carsten Albrecht, Roman Koch
    A dynamically reconfigurable packet-switched network-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:136-137 [Conf]
  5. Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
    On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:258- [Conf]
  6. Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner
    Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:584-589 [Conf]
  7. Jürgen Becker, Thilo Pionteck, Manfred Glesner
    DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:312-321 [Conf]
  8. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
    A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1090-1092 [Conf]
  9. Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
    A Framework for Teaching (Re)Configurable Architectures in Student Projects. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:444-451 [Conf]
  10. Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle
    An adaptive system-on-chip for network applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  11. Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
    Design of a reconfigurable AES encryption/decryption engine for mobile terminals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:545-548 [Conf]
  12. Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner
    The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:141-147 [Conf]
  13. Thilo Pionteck, N. Toender, Lukusa D. Kabulepa, Manfred Glesner, T. Kella
    On the Rapid Prototyping of Equalizers for OFDM Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:48-52 [Conf]
  14. Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
    Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:12-21 [Conf]
  15. Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
    Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:161-166 [Conf]
  16. Thilo Pionteck, Roman Koch, Carsten Albrecht
    Applying Partial Reconfiguration to Networks-On-Chips. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  17. Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker
    Communication Architectures for Dynamically Reconfigurable FPGA Designs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  18. Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle
    A Lightweight Framework for Runtime Reconfigurable System Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:61-64 [Conf]
  19. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
    On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:283-297 [Conf]
  20. Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
    Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:174-0 [Journal]

  21. Design and Simulation of Runtime Reconfigurable Systems. [Citation Graph (, )][DBLP]


  22. On the design parameters of runtime reconfigurable systems. [Citation Graph (, )][DBLP]


  23. Network processors. [Citation Graph (, )][DBLP]


  24. Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. [Citation Graph (, )][DBLP]


  25. WCET determination tool for embedded systems software. [Citation Graph (, )][DBLP]


Search in 0.034secs, Finished in 0.035secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002