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Soroush Abbaspour: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    Parameterized block-based non-gaussian statistical gate timing analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:947-952 [Conf]
  2. Soroush Abbaspour, Massoud Pedram
    Gate delay calculation considering the crosstalk capacitances. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:852-857 [Conf]
  3. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    Non-gaussian statistical interconnect timing analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:533-538 [Conf]
  4. Soroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer
    TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:19-24 [Conf]
  5. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:426-430 [Conf]
  6. Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer
    SACI: statistical static timing analysis of coupled interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:241-246 [Conf]
  7. Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
    Buffer sizing for minimum energy-delay product by using an approximating polynomial. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:112-115 [Conf]
  8. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    VGTA: Variation Aware Gate Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:351-356 [Conf]
  9. Soroush Abbaspour, Massoud Pedram, Payam Heydari
    Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:261-266 [Conf]
  10. Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap
    Fast Interconnect and Gate Timing Analysis for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1383-1388 [Journal]

  11. Driver waveform computation for timing analysis with multiple voltage threshold driver models. [Citation Graph (, )][DBLP]


  12. Towards a more physical approach to gate modeling for timing, noise, and power. [Citation Graph (, )][DBLP]


  13. A moment-based effective characterization waveform for static timing analysis. [Citation Graph (, )][DBLP]


  14. Efficient compression and handling of current source model library waveforms. [Citation Graph (, )][DBLP]


  15. Compact modeling of variational waveforms. [Citation Graph (, )][DBLP]


  16. Constrained aggressor set selection for maximum coupling noise. [Citation Graph (, )][DBLP]


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