Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 12

1. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1295-1308 [Journal]
   
2. Sumeer Goel, Ashok Kumar, Magdy A. Bayoumi
   Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1309-1321 [Journal]
   
3. Massimo Alioto, Gaetano Palumbo
   Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1322-1335 [Journal]
   
4. Mark M. Budnik, Kaushik Roy
   A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1336-1346 [Journal]
   
5. Erik J. Mentze, Herbert L. Hess, Kevin M. Buck, T. G. Windley
   A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1347-1353 [Journal]
   
6. Kambiz Rahimi, Chris Diorio
   Design and Application of Adaptive Delay Sequential Elements. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1354-1367 [Journal]
   
7. Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel
   Sequential Element Design With Built-In Soft Error Resilience. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1368-1378 [Journal]
   
8. C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, Y. Oowaki
   Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1379-1383 [Journal]
   
9. Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap
   Fast Interconnect and Gate Timing Analysis for Performance Optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1383-1388 [Journal]
   
10. José Luis Imaña, Román Hermida, Francisco Tirado
    Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1388-1393 [Journal]
    
11. Mosin Mondal, Yehia Massoud
    Accurate Loop Self Inductance Bound for Efficient Inductance Screening. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1393-1397 [Journal]