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Joseph T. Rahmeh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shien-Tai Pan, Kimming So, Joseph T. Rahmeh
    Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:76-84 [Conf]
  2. David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
    Automatic Generation of Behavioral Models from Switch-Level Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:179-184 [Conf]
  3. Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh
    Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:367-372 [Conf]
  4. Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham
    Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:393-396 [Conf]
  5. Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham
    TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:28-35 [Conf]
  6. Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham
    Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:9, pp:1132-1145 [Journal]
  7. Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham
    FAUST: An MOS Fault Simulator with Timing Information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:557-563 [Journal]

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