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Rajiv A. Ravindran:
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- Rajiv Ravindran, Rajat Moona
Retargetable Cache Simulation Using High Level Processor Models. [Citation Graph (0, 0)][DBLP] ACSAC, 2001, pp:114-129 [Conf]
- Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke
Systematic Register Bypass Customization for Application-Specific Processors. [Citation Graph (0, 0)][DBLP] ASAP, 2003, pp:64-74 [Conf]
- Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
Increasing the number of effective registers in a low-power processor using a windowed register file. [Citation Graph (0, 0)][DBLP] CASES, 2003, pp:125-136 [Conf]
- Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache. [Citation Graph (0, 0)][DBLP] CGO, 2005, pp:179-190 [Conf]
- Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. [Citation Graph (0, 0)][DBLP] CGO, 2004, pp:201-212 [Conf]
- Rajiv Ravindran, Rajat Moona
Retargetable Program Profiling Using High Level Processor Models. [Citation Graph (0, 0)][DBLP] HiPC, 2001, pp:224-236 [Conf]
- Michael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke
Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2004, v:24, n:3, pp:10-20 [Journal]
- Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2005, v:54, n:8, pp:998-1012 [Journal]
- Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1355-1371 [Journal]
- Rajiv Ravindran, Michael Chu, Scott A. Mahlke
Compiler-managed partitioned data caches for low power. [Citation Graph (0, 0)][DBLP] LCTES, 2007, pp:237-247 [Conf]
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. [Citation Graph (, )][DBLP]
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