Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 8

1. Joseph W. Jerome, Chi-Wang Shu
   Transport effects and characteristic modes in the modeling and simulation of submicron devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:917-923 [Journal]
   
2. Mark G. Graham, John J. Paulos, Douglas W. Nychka
   Template-based MOSFET device model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:924-933 [Journal]
   
3. Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker
   Datapath synthesis using a problem-space genetic algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:934-944 [Journal]
   
4. Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Jef L. van Meerbergen, Albert van der Werf
   Improved force-directed scheduling in high-throughput digital signal processing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:945-960 [Journal]
   
5. Jun Gu, Ruchir Puri
   Asynchronous circuit synthesis with Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:961-973 [Journal]
   
6. Bill Lin, Srinivas Devadas
   Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:974-985 [Journal]
   
7. Steven M. Nowick, David L. Dill
   Exact two-level minimization of hazard-free logic with multiple-input changes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:986-997 [Journal]
   
8. Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
   Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:998-1012 [Journal]
   
9. Mysore Sriram, Sung-Mo Kang
   Efficient approximation of the time domain response of lossy coupled transmission line trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1013-1024 [Journal]
   
10. Pranav Ashar, Sharad Malik
    Functional timing analysis using ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1025-1030 [Journal]
    
11. C. Y. Roger Chen, Cliff Yungchin Hou
    A pin permutation algorithm for improving over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1030-1037 [Journal]
    
12. D. Lambidonis, André Ivanov, Vinod K. Agarwal
    Fast signature computation for BIST linear compactors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1037-1044 [Journal]
    
13. Slawomir Pilarski
    Comments on "Test efficiency analysis of random self-test of sequential circuits". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1044-1045 [Journal]