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Ruchir Puri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ching-Te Chuang, Ruchir Puri
    SOI Digital CMOS VLSI - a Design Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:709-714 [Conf]
  2. Ruchir Puri, Jun Gu
    An Efficient algorithm for Microword Length Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:651-656 [Conf]
  3. Ruchir Puri, Jun Gu
    A Modular Partitioning Approach for Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:63-69 [Conf]
  4. Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
    Keeping hot chips cool. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:285-288 [Conf]
  5. Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
    Pushing ASIC performance in a power envelope. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:788-793 [Conf]
  6. Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
    Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:522-527 [Conf]
  7. Ruchir Puri, David S. Kung, Anthony D. Drumm
    Fast and accurate wire delay estimation for physical synthesis of large ASICs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:30-36 [Conf]
  8. Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri
    Design and CAD Challenges in sub-90nm CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:129-137 [Conf]
  9. David S. Kung, Ruchir Puri
    Optimal P/N width ratio selection for standard cell libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:178-184 [Conf]
  10. Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser
    Logic optimization by output phase assignment in dynamic logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:2-7 [Conf]
  11. David J. Frank, Ruchir Puri, Dorel Toma
    Design and CAD challenges in 45nm CMOS and beyond. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:329-333 [Conf]
  12. Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
    Wire density driven global routing for CMP variation and timing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:487-492 [Conf]
  13. Ruchir Puri, Jun Gu
    Area Efficient Synthesis of Asynchronous Interface Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:212-216 [Conf]
  14. Ruchir Puri, Jun Gu
    Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1686-1689 [Conf]
  15. Ruchir Puri, David S. Kung, Leon Stok
    Minimizing power with flexible voltage islands. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:21-24 [Conf]
  16. Ruchir Puri, Ching-Te Chuang
    Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:223-228 [Conf]
  17. Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim
    Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:153-158 [Conf]
  18. Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi
    Design of sub-90nm Circuits and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:3-4 [Conf]
  19. Ruchir Puri, Ching-Te Chuang
    SOI Digital Circuits: Design Issues. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:474-479 [Conf]
  20. Ruchir Puri, Tanay Karnik, Rajiv V. Joshi
    Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:5-7 [Conf]
  21. Ruchir Puri, Jun Gu
    A BDD SAT Solver for Satisfiability Testing: An Industrial Case Study. [Citation Graph (0, 0)][DBLP]
    Ann. Math. Artif. Intell., 1996, v:17, n:3-4, pp:315-337 [Journal]
  22. Louise Trevillyan, David S. Kung, Ruchir Puri, Lakshmi N. Reddy, Michael A. Kazda
    An Integrated Environment for Technology Closure of Deep-Submicron IC Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:14-22 [Journal]
  23. Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok
    Combinatorial cell design for CMOS libraries. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:1, pp:67-93 [Journal]
  24. Jun Gu, Ruchir Puri
    Asynchronous circuit synthesis with Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:961-973 [Journal]
  25. Ruchir Puri, Jun Gu
    An efficient algorithm to search for minimal closed covers in sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:737-745 [Journal]
  26. Ruchir Puri, Jun Gu
    Microword length minimization in microprogrammed controller synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1449-1457 [Journal]
  27. Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
    TROY: Track Router with Yield-driven Wire Planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:55-58 [Conf]
  28. Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian
    Making Manufacturing Work For You. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:107-108 [Conf]
  29. Kerry Bernstein, Paul Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steve Koester, John Magerlein, Ruchir Puri, Albert Young
    Interconnects in the Third Dimension: Design Challenges for 3D ICs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:562-567 [Conf]
  30. Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
    Is your layout density verification exact?: a fast exact algorithm for density calculation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:19-26 [Conf]
  31. Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
    Dummy fill density analysis with coupling constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:3-10 [Conf]

  32. CAD challenges for 3D ICs. [Citation Graph (, )][DBLP]


  33. Custom is from Venus and synthesis from Mars. [Citation Graph (, )][DBLP]


  34. Keeping hot chips cool: are IC thermal problems hot air? [Citation Graph (, )][DBLP]


  35. From milliwatts to megawatts: system level power challenge. [Citation Graph (, )][DBLP]


  36. Moore's Law: another casualty of the financial meltdown? [Citation Graph (, )][DBLP]


  37. History-based VLSI legalization using network flow. [Citation Graph (, )][DBLP]


  38. EDA challenges and options: investing for the future. [Citation Graph (, )][DBLP]


  39. DeltaSyn: An efficient logic difference optimizer for ECO synthesis. [Citation Graph (, )][DBLP]


  40. Logical and physical restructuring of fan-in trees. [Citation Graph (, )][DBLP]


  41. Will 22nm be our catch 22!: design and cad challenges. [Citation Graph (, )][DBLP]


  42. The Dawn of 22nm Era: Design and CAD Challenges. [Citation Graph (, )][DBLP]


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