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Sung-Mo Kang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang
    iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:548-551 [Conf]
  2. Abhijit Dharchoudhury, Sung-Mo Kang
    An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:704-709 [Conf]
  3. Abhijit Dharchoudhury, Sung-Mo Kang
    Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:154-158 [Conf]
  4. Tong Li, Sung-Mo Kang
    Layout Extraction and Verification Methodology CMOS I/O Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:291-296 [Conf]
  5. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Low-swing clock domino logic incorporating dual supply and dual threshold voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:467-472 [Conf]
  6. Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
    Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:732-737 [Conf]
  7. Jaewon Kim, Sung-Mo Kang
    An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:456-459 [Conf]
  8. Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang
    Domino logic synthesis minimizing crosstalk. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:280-285 [Conf]
  9. Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang
    VeriCDF: a new verification methodology for charged device failures. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:874-879 [Conf]
  10. Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang
    Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:549-554 [Conf]
  11. N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
    When bad things happen to good chips (panel session). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:736-737 [Conf]
  12. Yung-Ho Shih, Sung-Mo Kang
    ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:20-25 [Conf]
  13. Mysore Sriram, Sung-Mo Kang
    Fast Approximation of the Transient Response of Lossy Transmision Line Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:691-696 [Conf]
  14. Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang
    Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:752-757 [Conf]
  15. Ching-Han Tsai, Sung-Mo Kang
    Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:750-755 [Conf]
  16. Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
    Statistical Estimation of Average Power Dissipation in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:377-382 [Conf]
  17. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:260-267 [Conf]
  18. Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
    Logic Transformation for Low Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:158-162 [Conf]
  19. Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang
    Effective algorithms for cache-level compression. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:89-92 [Conf]
  20. Qiao Li, Sung-Mo Kang
    Technology independent arbitrary device extractor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:143-146 [Conf]
  21. Robert K. Grube, Qi Wang, Sung-Mo Kang
    Design limitations in deep sub-0.1µm CMOS SRAM. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:94-97 [Conf]
  22. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Transistor sizing for reliable domino logic design in dual threshold voltage technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:133-138 [Conf]
  23. Qiao Li, Sung-Mo Kang
    Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:183-188 [Conf]
  24. Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang
    NMOS Energy Recovery Logic. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:310-313 [Conf]
  25. Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
    2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:93-96 [Conf]
  26. Seung-Moon Yoo, Sung-Mo Kang
    No-Race Charge-Recycling Differential Logic (NCDL). [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:202-205 [Conf]
  27. Sueng-Yong Park, Vaduvur Bharghavan, Sung-Mo Kang
    Data Link Level Support for Handoff in Wireless ATM Network. [Citation Graph (0, 0)][DBLP]
    ICC (2), 1997, pp:765-769 [Conf]
  28. Yi-Kan Cheng, Sung-Mo Kang
    An efficient method for hot-spot identification in ULSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:124-127 [Conf]
  29. Abhijit Dharchoudhury, Sung-Mo Kang, H. Cha, J. H. Patel
    Fast timing simulation of transient faults in digital circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:719-722 [Conf]
  30. Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee
    Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:190-194 [Conf]
  31. Tanay Karnik, Sung-Mo Kang
    An empirical model for accurate estimation of routing delay in FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:328-331 [Conf]
  32. Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. (Dave) Liu, Sung-Mo Kang
    Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:318-321 [Conf]
  33. Jaewon Kim, Sung-Mo Kang
    A timing-driven data path layout synthesis with integer programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:716-719 [Conf]
  34. Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
    Implication graph based domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:111-114 [Conf]
  35. Tong Li, Ching-Han Tsai, Sung-Mo Kang
    Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:6-11 [Conf]
  36. Yusuf Leblebici, Sung-Mo Kang
    An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:400-403 [Conf]
  37. Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
    New Simulation Methods for MOS VLSI Timing and Reliability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:162-165 [Conf]
  38. Mysore Sriram, Sung-Mo Kang
    Detailed layer assignment for MCM routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:386-389 [Conf]
  39. Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang
    Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:366-370 [Conf]
  40. Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang
    High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:59-64 [Conf]
  41. Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
    Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:406-414 [Conf]
  42. Ashfaq Hossain, Sung-Mo Kang, Bob Horst
    Performance Comparison of Video Transport over ATM and ServerNet Interconnects. [Citation Graph (0, 0)][DBLP]
    ICMCS, 1997, pp:612-613 [Conf]
  43. Haoran Duan, John W. Lockwood, Sung-Mo Kang, J. D. Will
    A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1997, pp:20-28 [Conf]
  44. Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang
    1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:901-904 [Conf]
  45. Elizabeth J. Brauer, Sung-Mo Kang
    Functional Verification of ECL Circuits Including Voltage Regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1710-1713 [Conf]
  46. Elizabeth J. Brauer, Sung-Mo Kang
    Estimating Node Voltages in Bipolar Circuits Using Linear Programming. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:901-903 [Conf]
  47. Elizabeth J. Brauer, Sung-Mo Kang
    An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1580-1583 [Conf]
  48. Yi-Kan Cheng, Sung-Mo Kang
    Chip-Level Thermal Simulator to Predict VLSI Chip Temperature. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1392-1395 [Conf]
  49. Myong H. Cynn, Sung-Mo Kang
    Incremental Node Extraction Algorithms for Incremental Layout System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1691-1694 [Conf]
  50. Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang
    Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1389-1392 [Conf]
  51. Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan
    Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:1-6 [Conf]
  52. Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar
    High Performance CMOS Macromodule Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:179-182 [Conf]
  53. Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
    Feasible Region Approximation Using Convex Polytopes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1786-1789 [Conf]
  54. Ge Yang, Yong Sin Kim, Sung-Mo Kang
    Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5493-5496 [Conf]
  55. Q. Li, Sung-Mo Kang
    Trapezoid-to-simple polygon recomposition for resistance extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:495-498 [Conf]
  56. Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
    Full chip ESD design rule checking. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:503-506 [Conf]
  57. Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
    ESD design rule checker. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:499-502 [Conf]
  58. Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang
    Coupling-aware minimum delay optimization for domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:371-374 [Conf]
  59. Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
    New current-mode sense amplifiers for high density DRAM and PIM architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:938-941 [Conf]
  60. Chulwoo Kim, Kiwook Kim, Sung-Mo Kang
    Energy-efficient skewed static logic design with dual Vt. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:882-885 [Conf]
  61. Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
    Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:746-749 [Conf]
  62. Chulwoo Kim, Sung-Mo Kang
    A low-power reduced swing single clock flip-flop. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:806-809 [Conf]
  63. Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang
    Skew-tolerant high-speed (STHS) domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:154-157 [Conf]
  64. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Noise constrained power optimization for dual VT domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:158-161 [Conf]
  65. Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
    Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:1-4 [Conf]
  66. Jinghong Chen, Sung-Mo Kang
    Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:457-460 [Conf]
  67. Seung-Moon Yoo, Sung-Mo Kang
    CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:226-229 [Conf]
  68. Yi-Kan Cheng, Sung-Mo Kang
    Temperature-driven power and timing analysis for CMOS ULSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:214-217 [Conf]
  69. Jinghong Chen, Sung-Mo Kang
    A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:194-197 [Conf]
  70. Ching-Han Tsai, Sung-Mo Kang
    Macrocell placement with temperature profile optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:390-393 [Conf]
  71. Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
    A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:781-784 [Conf]
  72. Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang
    A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:53-56 [Conf]
  73. Anthony M. Hill, Sung-Mo Kang
    Determining accuracy bounds for simulation-based switching activity estimation. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:215-220 [Conf]
  74. Sung-Mo Kang
    Elements of low power design for integrated systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:205-210 [Conf]
  75. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware power optimization for on-chip interconnect. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:108-113 [Conf]
  76. Li-Pen Yuan, Sung-Mo Kang
    A sequential procedure for average power analysis of sequential circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:231-234 [Conf]
  77. Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
    Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:73-78 [Conf]
  78. Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang
    Interconnect thermal modeling for determining design limits on current density. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:172-178 [Conf]
  79. Sung-Mo Kang
    On-chip thermal engineering for peta-scale integration. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:76-76 [Conf]
  80. Ching-Han Tsai, Sung-Mo Kang
    Standard cell placement for even on-chip thermal distribution. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:179-184 [Conf]
  81. Ge Yang, Zhongda Wang, Sung-Mo Kang
    Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:421-424 [Conf]
  82. Yong Sin Kim, Sung-Mo Kang
    Programmable High Speed Multi-Level Simultaneous Bidirectional I/O. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:416-419 [Conf]
  83. Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang
    An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:80-86 [Conf]
  84. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Optimal Timing for Skew-Tolerant High-Speed Domino Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:41-46 [Conf]
  85. Anthony M. Hill, Sung-Mo Kang
    Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PPSN, 1994, pp:546-555 [Conf]
  86. Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang
    Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:261-0 [Conf]
  87. Ge Yang, Zhongda Wang, Sung-Mo Kang
    Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:222-227 [Conf]
  88. Jay R. Moorman, John W. Lockwood, Sung-Mo Kang
    Real-time prioritized call admission control in a base station scheduler. [Citation Graph (0, 0)][DBLP]
    WOWMOM, 2000, pp:28-37 [Conf]
  89. Jun Dong Cho, Majid Sarrafzadeh, Mysore Sriram, Sung-Mo Kang
    High-Performance MCM Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:27-37 [Journal]
  90. Brent K. Whitlock, Petar K. Pepeljugoski, Daniel M. Kuchta, John D. Crow, Sung-Mo Kang
    Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 1997, v:15, n:4, pp:717-730 [Journal]
  91. Elizabeth J. Brauer, Sung-Mo Kang
    An algorithm for functional verification of digital ECL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1546-1556 [Journal]
  92. H. Y. Chen, Sung-Mo Kang
    A new circuit optimization technique for high performance CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:670-677 [Journal]
  93. Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang
    Interconnect thermal modeling for accurate simulation of circuittiming and reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:197-205 [Journal]
  94. Yi-Kan Cheng, Sung-Mo Kang
    A temperature-aware simulation environment for reliable ULSI chipdesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1211-1220 [Journal]
  95. Yi-Kan Cheng, Prasun Raha, Chin-Chi Teng, Elyse Rosenbaum, Sung-Mo Kang
    ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:668-681 [Journal]
  96. Abhijit Dharchoudhury, Sung-Mo Kang
    Worst-case analysis and optimization of VLSI circuit performances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:481-492 [Journal]
  97. Carlos H. Díaz, Sung-Mo Kang
    New algorithms for circuit simulation of device breakdown. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1344-1354 [Journal]
  98. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
    Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:482-493 [Journal]
  99. Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici
    An accurate analytical delay model for BiCMOS driver circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:577-588 [Journal]
  100. Anthony M. Hill, Sung-Mo Kang
    Determining accuracy bounds for simulation-based switching activity estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:611-618 [Journal]
  101. D. K. Hwang, W. Kent Fuchs, Sung-Mo Kang
    An Efficient Approach to Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:802-809 [Journal]
  102. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Timing constraints for domino logic gates with timing-dependent keepers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:96-103 [Journal]
  103. Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law, Alexander D. Lopez
    Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:1, pp:18-29 [Journal]
  104. Ki-Wook Kim, Sung-Mo Kang
    Crosstalk noise minimization in domino logic design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1091-1100 [Journal]
  105. Jaewon Kim, Sung-Mo Kang
    A new triple-layer OTC channel router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1059-1070 [Journal]
  106. Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
    Domino logic synthesis based on implication graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:232-240 [Journal]
  107. Sung-Mo Kang
    Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:886-891 [Journal]
  108. Yusuf Leblebici, Sung-Mo Kang
    Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:235-246 [Journal]
  109. Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
    Chip-level charged-device modeling and simulation in CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:67-81 [Journal]
  110. Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang
    An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1621-1634 [Journal]
  111. Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
    Convexity-based algorithms for design centering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1536-1549 [Journal]
  112. Yung-Ho Shih, Sung-Mo Kang
    Analytic transient solution of general MOS circuit primitives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:719-731 [Journal]
  113. Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
    ILLIADS: a fast timing and reliability simulator for digital MOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1387-1402 [Journal]
  114. Mysore Sriram, Sung-Mo Kang
    Efficient approximation of the time domain response of lossy coupled transmission line trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1013-1024 [Journal]
  115. Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang
    iTEM: a temperature-dependent electromigration reliability diagnosis tool. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:882-893 [Journal]
  116. Richard W. Thaik, Ngee Lek, Sung-Mo Kang
    A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1479-1494 [Journal]
  117. Ching-Han Tsai, Sung-Mo Kang
    Cell-level placement for improving substrate thermal distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:253-266 [Journal]
  118. Tat-Kwan Yu, Sung-Mo Kang, I. N. Haji, Timothy N. Trick
    Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1013-1022 [Journal]
  119. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
    Minimum delay optimization for domino circuits - a coupling-aware approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:202-213 [Journal]
  120. Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
    Logic transformation for low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:265-283 [Journal]
  121. Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
    A 32-bit carry lookahead adder using dual-path all-N logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:992-996 [Journal]
  122. Sangho Shin, Kwyro Lee, Sung-Mo Kang
    2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  123. Yong Sin Kim, Sangho Shin, Sung-Mo Kang
    A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  124. Sangho Shin, Kwyro Lee, Sung-Mo Kang
    Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  125. Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
    Statistical estimation of average power dissipation using nonparametric techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:65-73 [Journal]
  126. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Noise constrained transistor sizing and power optimization for dual Vst domino logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:532-541 [Journal]
  127. Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
    Energy-efficient skewed static logic with dual Vt: design and synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:64-70 [Journal]
  128. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware interconnect power optimization in domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:79-89 [Journal]

  129. Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. [Citation Graph (, )][DBLP]


  130. 0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power. [Citation Graph (, )][DBLP]


  131. Design of a 6 bit 1.25 GS/s DAC for WPAN. [Citation Graph (, )][DBLP]


  132. A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O. [Citation Graph (, )][DBLP]


  133. Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages. [Citation Graph (, )][DBLP]


  134. New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. [Citation Graph (, )][DBLP]


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