Journals in DBLP

IEEE Trans. VLSI Syst.
2007, volume: 15, number: 7

1. Ka-Ming Keung, Vineela Manne, Akhilesh Tyagi
   A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:733-745 [Journal]
   
2. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
   Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:746-757 [Journal]
   
3. Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, J. Y. Choi
   Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:758-766 [Journal]
   
4. S.-P. Lin, C.-L. Lee, J.-E. Chen, J.-J. Chen, K.-L. Luo, W.-C. Wu
   A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:767-776 [Journal]
   
5. Seongmoon Wang
   A BIST TPG for Low Power Dissipation and High Fault Coverage. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:777-789 [Journal]
   
6. Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
   Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:790-800 [Journal]
   
7. Myoung-Cheol Shin, In-Cheol Park
   SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:801-810 [Journal]
   
8. Xinmiao Zhang
   Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:811-820 [Journal]
   
9. Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim
   Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:821-829 [Journal]
   
10. Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He
    Microarchitecture Configurations and Floorplanning Co-Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:830-841 [Journal]
    
11. Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
    Concurrent Error Detection in Reed-Solomon Encoders and Decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:842-846 [Journal]
    
12. Kuan-Hung Chen, Yuan-Sun Chu
    A Low-Power Multiplier With the Spurious Power Suppression Technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:846-850 [Journal]