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Tetsuya Higuchi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroaki Kitano, Tetsuya Higuchi
    High Performance Memory-Based Translation on IXM2 Massively Parallel Associative Memory Processor. [Citation Graph (1, 0)][DBLP]
    AAAI, 1991, pp:149-154 [Conf]
  2. Tetsuya Higuchi, Hiroaki Kitano, Tatsumi Furuya, Ken'ichi Handa, Akio Kokubu, Naoto Takahashi
    IXM2: A Parallel Associative Processor for Knowledge Processing. [Citation Graph (0, 0)][DBLP]
    AAAI, 1991, pp:296-303 [Conf]
  3. Isamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi
    An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller. [Citation Graph (0, 0)][DBLP]
    AAAI/IAAI, 1999, pp:182-187 [Conf]
  4. Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi
    Evolvable Hardware Chip for High Precision Printer Image Compression. [Citation Graph (0, 0)][DBLP]
    AAAI/IAAI, 1998, pp:486-491 [Conf]
  5. Masahiro Murakawa, Hirokazu Nosato, Tetsuya Higuchi
    Automatic Optical Fiber Alignment System Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    Artificial Evolution, 2003, pp:129-140 [Conf]
  6. Kozo Oi, Eiichiro Sumita, Osamu Furuse, Hitoshi Iida, Tetsuya Higuchi
    Real-Time Spoken Language Translation Using Associative Processors. [Citation Graph (0, 0)][DBLP]
    ANLP, 1994, pp:101-106 [Conf]
  7. Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi
    Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:204-207 [Conf]
  8. Mehrdad Salami, Hidenori Sakanashi, Masaharu Tanaka, Masaya Iwata, Takio Kurita, Tetsuya Higuchi
    On-Line Compression of High Precision Printer Images by Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1998, pp:219-228 [Conf]
  9. Neil Marston, Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi, Toshio Adachi, Kaoru Takasuka
    An Evolutionary Approach to GHz Digital Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2000, pp:125-132 [Conf]
  10. Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi
    Power Dissipation Reductions with Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2003, pp:111-116 [Conf]
  11. Didier Keymeulen, Masaya Iwata, Kenji Konaka, Ryouhei Suzuki, Yasuo Kuniyoshi, Tetsuya Higuchi
    Off-Line Model-Free and On-Line Model-Based Evolution for Tracking Navigation Using Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    EvoRobots, 1998, pp:211-226 [Conf]
  12. Didier Keymeulen, Kenji Konaka, Masaya Iwata, Yasuo Kuniyoshi, Tetsuya Higuchi
    Robot Learning Using Gate-Level Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    EWLR, 1997, pp:173-0 [Conf]
  13. Tetsuya Higuchi, Tatsumi Furuya, Hiroyuki Kusumoto, Ken'ichi Handa, Akio Kokubu
    The IX Supercomputer for Knowledge-Based Systems. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:1041-1048 [Conf]
  14. Yasuo Takehisa, Hidenori Sakanashi, Tetsuya Higuchi
    Adaptive Wavelet Transform for Lossless Compression using Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    GECCO, 2000, pp:259-266 [Conf]
  15. Isamu Kajitani, Tsutomu Hoshino, Masaya Iwata, Tetsuya Higuchi
    Variable Length Chromosome GA for Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    International Conference on Evolutionary Computation, 1996, pp:443-447 [Conf]
  16. Hidenori Sakanashi, Tetsuya Higuchi, Hitoshi Iba, Yukinori Kakazu
    An Approach for Genetic Synthesizer of Binary Decision Diagram. [Citation Graph (0, 0)][DBLP]
    International Conference on Evolutionary Computation, 1996, pp:559-564 [Conf]
  17. Hitoshi Iba, Masaya Iwata, Tetsuya Higuchi
    Machine Learning Approach to Gate-Level Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:327-343 [Conf]
  18. Weixin Liu, Masahiro Murakawa, Tetsuya Higuchi
    ATM Cell Scheduling by Function Level Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:180-192 [Conf]
  19. Bernard Manderick, Tetsuya Higuchi
    Evolvable Hardware: An Outlook. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:305-311 [Conf]
  20. Masahiro Murakawa, Shuji Yoshizawa, Toshio Adachi, Shiro Suzuki, Kaoru Takasuka, Masaya Iwata, Tetsuya Higuchi
    Analogue EHW Chip for Intermediate Frequency Filters. [Citation Graph (0, 0)][DBLP]
    ICES, 1998, pp:134-143 [Conf]
  21. Masahiro Murakawa, Shuji Yoshizawa, Tetsuya Higuchi
    Adaptive Equalization of Digital Communication Channels Using Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:379-389 [Conf]
  22. Hirokazu Nosato, Yuji Kasai, Taro Itatani, Masahiro Murakawa, Tatsumi Furuya, Tetsuya Higuchi
    Evolvable Optical Systems and Their Applications. [Citation Graph (0, 0)][DBLP]
    ICES, 2001, pp:327-340 [Conf]
  23. Didier Keymeulen, Marc Durantez, Kenji Konaka, Yasuo Kuniyoshi, Tetsuya Higuchi
    An Evolutionary Robot Navigation System Using a Gate-Level Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:195-209 [Conf]
  24. Tetsuya Higuchi, Masaya Iwata, Isamu Kajitani, Hitoshi Iba, Yuji Hirao, Tatsumi Furuya, Bernard Manderick
    Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP]
    Towards Evolvable Hardware, 1995, pp:118-135 [Conf]
  25. Masaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi
    Implementation of a Gate-Level Evolvable Hardware Chip. [Citation Graph (0, 0)][DBLP]
    ICES, 2001, pp:38-49 [Conf]
  26. Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shougo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi
    A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. [Citation Graph (0, 0)][DBLP]
    ICES, 1998, pp:1-12 [Conf]
  27. Yuji Kasai, Hidenori Sakanashi, Masahiro Murakawa, Shogo Kiryu, Neil Marston, Tetsuya Higuchi
    Initial Evaluation of an Evolvable Microwave Circuit. [Citation Graph (0, 0)][DBLP]
    ICES, 2000, pp:103-112 [Conf]
  28. Yuji Kasai, Eiichi Takahashi, Masaya Iwata, Yosuke Iijima, Hidenori Sakanashi, Masahiro Murakawa, Tetsuya Higuchi
    Adaptive Waveform Control in a Data Transceiver for Multi-speed IEEE1394 and USB Communication. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:198-204 [Conf]
  29. Hidenori Sakanashi, Tetsuya Higuchi, Hitoshi Iba, Yukinori Kakazu
    Evolution of Binary Decision Diagrams for Digital Circuit Design Using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:470-481 [Conf]
  30. Hidenori Sakanashi, Masaya Iwata, Tetsuya Higuchi
    A Lossless Compression Method for Halftone Images Using Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 2001, pp:314-326 [Conf]
  31. Mehrdad Salami, Masahiro Murakawa, Tetsuya Higuchi
    Data Compression Based on Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:169-179 [Conf]
  32. Masaharu Tanaka, Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Takio Kurita, Tetsuya Higuchi
    Data Compression for Digital Color Electrophotographic Printer with Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1998, pp:106-114 [Conf]
  33. Xin Yao, Tetsuya Higuchi
    Promises and Challenges of Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:55-78 [Conf]
  34. Hiroaki Kitano, Stephen F. Smith, Tetsuya Higuchi
    GA-1: A Parallel Associative Memory Processor for Rule Learning with Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICGA, 1991, pp:311-317 [Conf]
  35. Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tetsuya Higuchi
    On-line Adaptation of Neural Networks with Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICGA, 1997, pp:792-800 [Conf]
  36. Masahiro Murakawa, Kazuyuki Hiraoka, Tetsuya Higuchi, Tatsumi Furuya, Shuji Yoshizawa
    Adaptive Blind Equalization Using Bottleneck Networks Implemented by Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICONIP, 1998, pp:89-92 [Conf]
  37. Tetsuya Higuchi, Tatsumi Furuya, Hiroyuki Kusumoto, Ken'ichi Handa, Akio Kokubu
    The Prototype of a Semantic Network Machine IXM. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:217-224 [Conf]
  38. Hitoshi Iba, Tetsuya Higuchi, Hugo de Garis, Taisuke Sato
    Evolutionary Learning Strategy using Bug-Based Search. [Citation Graph (0, 0)][DBLP]
    IJCAI, 1993, pp:960-966 [Conf]
  39. Hiroaki Kitano, Tetsuya Higuchi
    Massively Parallel Memory-Based Parsing. [Citation Graph (0, 0)][DBLP]
    IJCAI, 1991, pp:918-924 [Conf]
  40. Hiroaki Kitano, James A. Hendler, Tetsuya Higuchi, Dan I. Moldovan, David L. Waltz
    Massively Parallel Artificial Intelligence. [Citation Graph (0, 0)][DBLP]
    IJCAI, 1991, pp:557-562 [Conf]
  41. Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tetsuya Higuchi
    Evolvable Hardware for Generalized Neural Networks. [Citation Graph (0, 0)][DBLP]
    IJCAI, 1997, pp:1146-1155 [Conf]
  42. Eiichiro Sumita, Kozo Oi, Osamu Furuse, Hitoshi Iida, Tetsuya Higuchi, Naoto Takahashi, Hiroaki Kitano
    Example-Based Machine Translation on Massively Parallel Processors. [Citation Graph (0, 0)][DBLP]
    IJCAI, 1993, pp:1283-1289 [Conf]
  43. Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, Naoto Takahashi, Hiroyasu Nishiyama, Akio Kokubu
    IXM2: A Parallel Associative Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:22-31 [Conf]
  44. Tatsumi Furuya, Tetsuya Higuchi, Hiroyuki Kusumoto, Ken'ichi Handa, Akio Kokubu
    Architectural Evaluation of a Semantic Network Machine. [Citation Graph (0, 0)][DBLP]
    IWDM, 1987, pp:544-556 [Conf]
  45. Tetsuya Higuchi, Hitoshi Iba, Bernard Manderick
    Applying Evolvable Hardware to Autonomous Agents. [Citation Graph (0, 0)][DBLP]
    PPSN, 1994, pp:524-533 [Conf]
  46. Hitoshi Iba, Sumitaka Akiba, Tetsuya Higuchi, Taisuke Sato
    BUGS: A Bug-Based Search Strategy using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    PPSN, 1992, pp:167-0 [Conf]
  47. Masaya Iwata, Isamu Kajitani, Hitoshi Yamada, Hitoshi Iba, Tetsuya Higuchi
    A Pattern Recognition System Using Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:761-770 [Conf]
  48. Yong Liu, Masaya Iwata, Tetsuya Higuchi, Didier Keymeulen
    An Integrated On-Line Learning System for Evolving Programmable Logic Array Controllers. [Citation Graph (0, 0)][DBLP]
    PPSN, 2000, pp:589-598 [Conf]
  49. Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tatsumi Furuya, Masaya Iwata, Tetsuya Higuchi
    Hardware Evolution at Function Level. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:62-71 [Conf]
  50. Masahiro Murakawa, Eiichi Takahashi, Tatsuya Susa, Tetsuya Higuchi
    Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins. [Citation Graph (0, 0)][DBLP]
    SMC (4), 2004, pp:3670-3674 [Conf]
  51. Hirokazu Nosato, Taro Itatani, Masahiro Murakawa, Tetsuya Higuchi, Hitoshi Noguchi
    Automatic wave-front correction of a femtosecond laser using genetic algorithm. [Citation Graph (0, 0)][DBLP]
    SMC (4), 2004, pp:3675-3679 [Conf]
  52. Hirokazu Nosato, Masahiro Murakawa, Tetsuya Higuchi
    Automatic Alignment of Multiple Optical Components Using Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:67-73 [Conf]
  53. Didier Keymeulen, Masaya Iwata, Yasuo Kuniyoshi, Tetsuya Higuchi
    Online Evolution for a Self-Adapting Robotic Navigation System Using Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    Artificial Life, 1998, v:4, n:4, pp:359-393 [Journal]
  54. Tetsuya Higuchi, Nobuki Kajihara
    Evolvable Hardware Chips for Industrial Applications. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1999, v:42, n:4, pp:60-66 [Journal]
  55. Tetsuya Higuchi, Ken'ichi Handa, Naoto Takahashi, Tatsumi Furuya, Hitoshi Iida, Eiichiro Sumita, Kozo Oi, Hiroaki Kitano
    The IXM2 Parallel Associative Processor for AI. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:11, pp:53-63 [Journal]
  56. Ian Frank, Bernard Manderick, Tetsuya Higuchi
    Recent Advances in Evolvable Systems - ICES 96 (International Conference on Evolvable Systems). [Citation Graph (0, 0)][DBLP]
    Evolutionary Computation, 1997, v:5, n:1, pp:105-114 [Journal]
  57. Didier Keymeulen, Masaya Iwata, Kenji Konaka, Yasuo Kuniyoshi, Tetsuya Higuchi
    Evolvable Hardware: A Robot Navigation System Testbed. [Citation Graph (0, 0)][DBLP]
    New Generation Comput., 1998, v:16, n:2, pp:97-122 [Journal]
  58. Masaya Iwata, Isamu Kajitani, Masahiro Murakawa, Yuji Hirao, Hitoshi Iba, Tetsuya Higuchi
    Pattern recognition system using evolvable hardware. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2000, v:31, n:4, pp:1-11 [Journal]
  59. Masahiro Murakawa, Yoshihiro Noda, Tetsuya Higuchi
    An automatic fiber alignment system using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2004, v:35, n:11, pp:80-90 [Journal]
  60. Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi
    The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:6, pp:628-639 [Journal]
  61. Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu
    Real-world applications of analog and digital evolvable hardware . [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 1999, v:3, n:3, pp:220-235 [Journal]
  62. Yong Liu, Xin Yao, Tetsuya Higuchi
    Evolutionary ensembles with negative correlation learning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2000, v:4, n:4, pp:380-387 [Journal]
  63. Xin Yao, Tetsuya Higuchi
    Promises and challenges of evolvable hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part C, 1999, v:29, n:1, pp:87-97 [Journal]

  64. Adaptive Optical Proximity Correction Using an Optimization Method. [Citation Graph (, )][DBLP]


  65. Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins. [Citation Graph (, )][DBLP]


  66. Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation. [Citation Graph (, )][DBLP]


  67. World-Wide Accessible LDPC Encoder/Decoder Generator Using Web-Based GUI and API. [Citation Graph (, )][DBLP]


  68. Proposal of transmission line modeling using multi-objective optimization techniques. [Citation Graph (, )][DBLP]


  69. Anomalousness Detection for Surgery Videos Using CHLAC Feature. [Citation Graph (, )][DBLP]


  70. Recognition of Dynamic Texture Patterns Using CHLAC Features. [Citation Graph (, )][DBLP]


  71. Histopathological Diagnostic Support Technology Using Higher-Order Local Autocorrelation Features. [Citation Graph (, )][DBLP]


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