SCEAS

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Yiannos Manoli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Friedel Gerfers, Yiannos Manoli
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters. [Citation Graph (0, 0)][DBLP]
DATE, 2001, pp:361-369 [Conf]
Ruimin Huang, Yiannos Manoli
Phased Array and Adaptive Antenna Transceivers in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
DSD, 2004, pp:587-592 [Conf]
S. Jayapal, S. Ramachandran, R. Bhutada, Yiannos Manoli
Optimization of Electronic Power Consumption in Wireless Sensor Nodes. [Citation Graph (0, 0)][DBLP]
DSD, 2005, pp:165-169 [Conf]
Rolf Hakenes, Yiannos Manoli
A Segmented Gray Code for Low-Power Microcontroller Address Buses. [Citation Graph (0, 0)][DBLP]
EUROMICRO, 1999, pp:1240-1243 [Conf]
Rolf Hakenes, Yiannos Manoli
A Novel Low-Power Microprocessor Architecture. [Citation Graph (0, 0)][DBLP]
ICCD, 2000, pp:141-146 [Conf]
Rolf Hakenes, Yiannos Manoli
Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter. [Citation Graph (0, 0)][DBLP]
ICCD, 1999, pp:277-278 [Conf]
Joachim Becker, Yiannos Manoli
A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable G/sub M/-cells. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2004, pp:1092-1095 [Conf]
Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
A 1 V, 12-bit wideband continuous-time /spl Sigma//spl Delta/ modulator for UMTS applications. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2003, pp:921-924 [Conf]
Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2004, pp:1076-1079 [Conf]
Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
A new technique for automatic error correction in Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (3), 2005, pp:2539-2542 [Conf]
Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli
Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed. [Citation Graph (0, 0)][DBLP]
ISCAS (3), 2005, pp:2543-2546 [Conf]
Matthias Keller, Yiannos Manoli, Friedel Gerfers
A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2004, pp:289-292 [Conf]
Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2003, pp:925-928 [Conf]
Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2003, pp:1037-1040 [Conf]
Maurits Ortmanns, Markus Kuderer, Yiannos Manoli, Friedel Gerfers
A cascaded continuous-time Sigma Delta modulator with 80 dB dynamic range. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2004, pp:405-408 [Conf]
Lourans Samid, Patrick Volz, Yiannos Manoli
A dynamic analysis of a latched CMOS comparator. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2004, pp:181-184 [Conf]
Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
On the synthesis of cascaded continuous-time Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2001, pp:419-422 [Conf]
Lourans Samid, Maurits Ortmanns, Yiannos Manoli, Friedel Gerfers
A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulator. [Citation Graph (0, 0)][DBLP]
ISCAS (3), 2002, pp:293-296 [Conf]
Maurits Ortmanns, Lourans Samid, Yiannos Manoli, Friedel Gerfers
Multirate cascaded continuous time Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (4), 2002, pp:225-228 [Conf]
Friedel Gerfers, Kian Min Soh, Maurits Ortmanns, Yiannos Manoli
Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
ISCAS (4), 2002, pp:233-236 [Conf]
Friedel Gerfers, Yiannos Manoli
A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session). [Citation Graph (0, 0)][DBLP]
ISLPED, 2000, pp:219-221 [Conf]
Joachim Becker, Fabian Henrici, Yiannos Manoli
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array. [Citation Graph (0, 0)][DBLP]
IWSOC, 2005, pp:434-438 [Conf]
Joachim Becker, Yiannos Manoli
Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
FPL, 2006, pp:1-4 [Conf]
Joachim Becker, Stanis Trendelenburg, Fabian Henrici, Yiannos Manoli
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm. [Citation Graph (0, 0)][DBLP]
GECCO, 2007, pp:190-197 [Conf]
Matthias Keller, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli
A Method for the Discrete-Time Simulation of Continuous-Time Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP]
ISCAS, 2007, pp:241-244 [Conf]
Matthias Keller, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli
On the Implicit Anti-Aliasing Feature of Continuous-Time Multistage Noise-Shaping Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP]
ISCAS, 2007, pp:721-724 [Conf]
Alexander Buhmann, Matthias Keller, Maurits Ortmanns, Yiannos Manoli
Estimating Circuit Nonidealities of Continuous-Time Multibit Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP]
ISCAS, 2007, pp:2264-2267 [Conf]
Fabian Henrici, Joachim Becker, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli
A Continuous-Time Field Programmable Analog Array Using Parasitic Capacitance Gm-C Filters. [Citation Graph (0, 0)][DBLP]
ISCAS, 2007, pp:2236-2239 [Conf]
C. Peters, O. Kessling, Fabian Henrici, Maurits Ortmanns, Yiannos Manoli
CMOS Integrated Highly Efficient Full Wave Rectifier. [Citation Graph (0, 0)][DBLP]
ISCAS, 2007, pp:2415-2418 [Conf]
Lourans Samid, Yiannos Manoli
A multibit continuous time sigma delta modulator with successive-approximation quantizer. [Citation Graph (0, 0)][DBLP]
ISCAS, 2006, pp:- [Conf]
Yiannos Manoli
Special section on the 2001 International Conference on Computer Design (ICCD). [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:301-302 [Journal]
Timing modeling for digital sub-threshold circuits. [Citation Graph (, )][DBLP]
On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip. [Citation Graph (, )][DBLP]
Hardware-software-codesign of application specific microcontrollers with the ASM environment. [Citation Graph (, )][DBLP]
A GP algorithm for efficient synthesis of GM-C filters on a hexagonal FPAA structure. [Citation Graph (, )][DBLP]
A Study on self-timed asynchronous subthreshold logic. [Citation Graph (, )][DBLP]
A rapid prototyping environment for high-speed reconfigurable analog signal processing. [Citation Graph (, )][DBLP]
A low power and low voltage continuous time /spl Sigma//spl Delta/ modulator. [Citation Graph (, )][DBLP]
A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs. [Citation Graph (, )][DBLP]
Analysis of digital gain error compensation in continuous-time cascaded sigma-delta modulators. [Citation Graph (, )][DBLP]
High-bandwidth floating gate CMOS rectifiers with reduced voltage drop. [Citation Graph (, )][DBLP]
Variability of flip-flop timing at sub-threshold voltages. [Citation Graph (, )][DBLP]
A novel 0.5 V 15 µW 1.3 MHz temperature-compensated analog PWM-controller for switch-mode converters. [Citation Graph (, )][DBLP]
A field programmable Gm-C filter array (FPAA) for online adaptation to environmental changes. [Citation Graph (, )][DBLP]

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