Conferences in DBLP
Pierre G. Paulin Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia Application. [Citation Graph (0, 0)][DBLP ] Conf ] Kresimir Mihic , Tajana Simunic , Giovanni De Micheli Reliability and Power Management of Integrated Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhat Mishra , Nikil D. Dutt Functional Validation of Programmable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Amine Jerraya Long Term Trends for Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Nebel System-Level Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak Life-Inspired Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco J. Cazorla , Peter M. W. Knijnenburg , Rizos Sakellariou , Enrique Fernández , Alex Ramírez , Mateo Valero Implicit vs. Explicit Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ulf Schlichtmann Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto R. Osorio , Javier D. Bruguera Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmet Bindal , Silvio Brugada , T. Ha , Willie Sana , Mandeep Singh , Vinilkant Tejaswi , David Wyland A Simple Micro-Threaded Data-Driven Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Turgay Temel , Avni Morgul , Nizamettin Aydin A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gwenolé Corre , Eric Senn , Nathalie Julien , Eric Martin Memory Aware HLS and the Implementation of Ageing Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Marteil , Nathalie Julien , Eric Senn , Eric Martin A Complete Methodology for Memory Optimization in DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] P. D. Hyde , G. Russell ASSEC: An Asynchronous Self-Checking RISC-based Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Huibin Shi , Chris Bailey Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Bailey A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Soyeb Alli , Chris Bailey Compiler-Directed Dynamic Memory Disambiguation for Loop Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Rawski , Henry Selvaraj , Pawel Morawiecki Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Maik Boden , Manfred Koegst , José Luis Tiburcio Badía , Steffen Rülke Cost-Efficient Implementation of Adaptive Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Fiser , Hana Kubatova Boolean Minimizer FC-Min: Coverage Finding Process. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Dominik Gawlowski , Aleksander Slusarczyk An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Görschwin Fey , Junhao Shi , Rolf Drechsler BDD Circuit Optimization for Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Pasquale Ciao , Giulio Colavolpe , Luca Fanucci A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Fanucci , Riccardo Locatelli , Esa Petri VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Jayapreetha Natesan , Damu Radhakrishnan Shift Invert Coding (SINV) for Low Power VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey McFiggins , Marie Yvanoff , Jayanti Venkataraman Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jussi Roivainen , Jukka Rautio IP-Block Based Integration of Very High Performance WLAN Modem. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Chaves , Leonel Sousa {2n +1, sn+k , sn -1}: A New RNS Moduli Set Extension. [Citation Graph (0, 0)][DBLP ] Conf ] Muthukumar Venkatesan , Daggu Venkateshwar Rao Image Processing Algorithms on Reconfigurable Architecture using HandelC. [Citation Graph (0, 0)][DBLP ] Conf ] Imed Aouadi , Omar Hammami Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder. [Citation Graph (0, 0)][DBLP ] Conf ] Suleyman Malki , Lambert Spaanenburg On the Packet-Switched Implementation of a Discrete-Time CNN. [Citation Graph (0, 0)][DBLP ] Conf ] Luo Jianwen , Jong Ching Chuen Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Umut Küçükkabak , Ahmet Akkas Design and Implementation of Reciprocal Unit Using Table Look-up and Newton-Raphson Iteration. [Citation Graph (0, 0)][DBLP ] Conf ] Faisal M. Khan , Mark G. Arnold , William M. Pottenger Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ali R. Iranpour , Krzysztof Kuchcinski Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4. [Citation Graph (0, 0)][DBLP ] Conf ] Qubo Hu , Martin Palkovic , Per Gunnar Kjeldsberg Memory Requirement Optimization with Loop Fusion and Loop Shifting. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod Viswanath Multi-log Processor - Towards Scalable Event-Driven Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Szymon Bieganski Information Trans-Coders in Information-Driven Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] S. F. Nielsen , Jens Sparsø , Jan Madsen Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Wolinski , Krzysztof Kuchcinski , Maya Gokhale A Constraints Programming Approach to Communication Scheduling on SoPC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Salim Ouadjaout , Dominique Houzet Easy SoC Design with VCI SystemC Adapters. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander A. Petrovsky , Sergei L. Shkredov Multi-Pipeline Implementations of Real-Time Vector DFT. [Citation Graph (0, 0)][DBLP ] Conf ] Filippo Speziali , Julien Zory Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , Abdelhalim Alsharqawi Pipeline-Level Control of Self-Resetting Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Mars Lan , Morteza Biglari-Abhari An Energy-Efficient Adaptive Multiple-Issue Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Refik Sever , A. Neslin Ismailoglu , Yusuf Çagatay Tekmen , Murat Askar , Burak Okcan A High Speed FPGA Implementation of the Rijndael Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Cao Cao , Bengt Oelmann Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Karlsson , Petru Eles , Zebo Peng A Formal Verification Methodology for IP-based Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Haridimos T. Vergos , Costas Efstathiou Diminished-1 Modulo 2n + 1 Squarer Design. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslaw Jablonski , Marek Gorgon Handel-C implementation of Classical Component Labelling Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] David Elléouet , Nathalie Julien , Dominique Houzet , J.-G. Cousin , Eric Martin Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Dietterle , Jerzy Ryman , Kai F. Dombrowski , Rolf Kraemer Mapping of High-Level SDL Models to Efficient Implementations for TinyOS. [Citation Graph (0, 0)][DBLP ] Conf ] Abdil Rashid Mohamed , Zebo Peng , Petru Eles A Heuristic for Wiring-Aware Built-In Self-Test Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander V. Drozd , R. Al-Azzeh , J. V. Drozd , M. V. Lobachev The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data. [Citation Graph (0, 0)][DBLP ] Conf ] Iosif Antochi , Ben H. H. Juurlink , Stamatis Vassiliadis , Petri Liuha Scene Management Models and Overlap Tests for Tile-Based Rendering. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Gawkowski , Janusz Sosnowski Evaluation of Transient Fault Susceptibility in Microprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Hahanov , Irina Hahanova , Stanley Hyduke Topological BDP Fault Simulation Method. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Shojaei , Habib Ghayoumi Techniques for Formal Verification of Digital Systems: A System Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Salvatore Vitabile , Antonio Gentile , Sabato Marco Siniscalchi , Filippo Sorbello Efficient Rapid Prototyping of Image and Video Processing Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Prain , Andrew P. Paplinski A Distributed Arithmetic Online Rotator for Signal Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Radek Dobias , Hana Kubatova FPGA Based Design of the Railway's Interlocking Equipments. [Citation Graph (0, 0)][DBLP ] Conf ] Víctor Reyes , Tomás Bautista , Gustavo Marrero , Pedro P. Carballo , Wido Kruijtzer CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Liam Noonan , Colin Flanagan Modeling a Network Processor Using Object Oriented Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolay Kavaldjiev , Gerard J. M. Smit An Energy-Efficient Network-on-Chip for a Heterogeneous Tiled Reconfigurable Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislav Korbel , Vlastimil Jánes Interesting Applications of Atmel AVR Microcontrollers. [Citation Graph (0, 0)][DBLP ] Conf ] Jung-Yup Kang , Jean-Luc Gaudiot A Fast and Well-Structured Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Luiza de Macedo Mourelle , Nadia Nedjah Fast Reconfigurable Hardware for the M-ary Modular Exponentiation. [Citation Graph (0, 0)][DBLP ] Conf ] Kuspriyanto , Yusrila Y. Kerlooza Towards New Real-Time Processor: The Multioperand MSB-First Real-Time Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Jari Kreku , Jani Penttilä , Janne Kangas , Juha-Pekka Soininen Workload Simulation Method for Evaluation of Application Feasibility in a Mobile Multiprocessor Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Blunno , Guy Alain Narboni , Claudio Passerone An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design. [Citation Graph (0, 0)][DBLP ] Conf ] Chichyang Chen , Kuo-Sheng Cheng An Efficient Exponential Algorithm with Exponential Convergence Rate. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Trancoso What to Adapt in a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Handy , Frank Grassert , Dirk Timmermann DCP: A New Data Collection Protocol for Bluetooth-Based Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhong Li , Laxmi Gewali , Henry Selvaraj , Muthukumar Venkatesan Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew D'Souza , Adam Postula Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Ruimin Huang , Yiannos Manoli Phased Array and Adaptive Antenna Transceivers in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Abey Abraham Cohen Addressing architecture for Brain-like Massively Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Soyeb Alli , Chris Bailey A Mechanism for Implementing Precise Exceptions in Pipelined Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Moinul Islam Zaber , Md. Mazder Rahman , Md. Rafiqul Islam Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Kugan Vivekanandarajah , Thambipillai Srikanthan , Saurav Bhattacharyya Dynamic Filter Cache for Low Power Instruction Memory Hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad K. Akbari , Ali Jahanian , Mohsen Naderi , Bahman Javadi Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Chirca , Michael J. Schulte , John Glossner , Haoran Wang , Suman Mamidi , Pablo I. Balzola , Stamatis Vassiliadis A Static Low-Power, High-Performance 32-bit Carry Skip Adder. [Citation Graph (0, 0)][DBLP ] Conf ] J. D. Kranthi Kumar , S. Srinivasan A Novel VLSI Architecture to Implement Region Merging Algorithm for Image Segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Maria J. Avedillo , José M. Quintana A Threshold Logic Synthesis Tool for RTD Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 