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Publications of Author

1. David Bedrosian, Jiri Vlach
   An Accelerated Steady-State Method for Networks with Internally Controlled Switches. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1991, pp:24-27 [Conf]
   
2. Francisco V. Fernández, Georges G. E. Gielen, Lawrence Huelsman, Agnieszka Konczykowska, Stefano Manetti, Willy M. C. Sansen, Jiri Vlach
   Pleasures, Perils and Pitfalls of Symbolic Analysis. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:451-457 [Conf]
   
3. Kumaraswamy Ponnambalam, Abbas Seifi, Jiri Vlach
   Yield optimization with correlated design parameters and non-symmetrical marginal distributions. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2003, pp:736-739 [Conf]
   
4. Juraj Valsa, Jiri Vlach
   SWANN - A Program for Analysis of Switched Analog Nonlinear Networks. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:1752-1755 [Conf]
   
5. Jiri Vlach, Ajoy Opal, Jacek Wojciechowski
   Simulation of Networks with Inconsistent Initial Conditions. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:1627-1630 [Conf]
   
6. Jacek Wojciechowski, Jiri Vlach
   Spectra of Graphs with Circulant Blocks and their Applications. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:161-164 [Conf]
   
7. C.-J. Richard Shi, Anthony Vannelli, Jiri Vlach
   Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning. [Citation Graph (0, 0)][DBLP]
   J. Heuristics, 1997, v:3, n:3, pp:225-243 [Journal]
   
8. James A. Barby, Jiri Vlach, Kishore Singhal
   Polynomial splines for MOSFET model approximation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:5, pp:557-566 [Journal]
   
9. Rakesh Chadha, Kishore Singhal, Jiri Vlach, Ernst Christen, Milan Vlach
   WATOPT -- An Optimizer for Circuit Applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:472-479 [Journal]
   
10. Ernst Christen, Jiri Vlach
    NETOPT-a program for multiobjective design of linear networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:5, pp:567-577 [Journal]
    
11. Genhong Ruan, Jiri Vlach, James A. Barby
    Current-limited switch-level timing simulator for MOS logic networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:659-667 [Journal]
    
12. Genhong Ruan, Jiri Vlach, James A. Barby
    Logic simulation with current-limited switches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:133-141 [Journal]
    
13. Genhong Ruan, Jiri Vlach, James A. Barby, Ajoy Opal
    Analog functional simulator for multilevel systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:565-576 [Journal]
    
14. Abbas Seifi, Kumaraswamy Ponnambalam, Jiri Vlach
    Probabilistic design of integrated circuits with correlated input parameters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1214-1219 [Journal]
    
15. Jiri Vlach, James A. Barby, Anthony Vannelli, T. Talkhan, C.-J. Richard Shi
    Group delay as an estimate of delay in logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:949-953 [Journal]
    
16. Jacek Wojciechowski, Jiri Vlach
    Ellipsoidal method for design centering and yield estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1570-1579 [Journal]