The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Abhishek Ranjan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Abhishek Ranjan, Ravin Balakrishnan, Mark H. Chignell
    Searching in audio: the utility of transcripts, dichotic presentation, and time-compression. [Citation Graph (0, 0)][DBLP]
    CHI, 2006, pp:721-730 [Conf]
  2. Steve Tsang, Ravin Balakrishnan, Karan Singh, Abhishek Ranjan
    A suggestive interface for image guided 3D sketching. [Citation Graph (0, 0)][DBLP]
    CHI, 2004, pp:591-598 [Conf]
  3. Abhishek Ranjan, Jeremy P. Birnholtz, Ravin Balakrishnan
    Dynamic shared visual spaces: experimenting with automatic camera control in a remote repair task. [Citation Graph (0, 0)][DBLP]
    CHI, 2007, pp:1177-1186 [Conf]
  4. Abhishek Ranjan, Jeremy P. Birnholtz, Ravin Balakrishnan
    An exploratory analysis of partner action and camera control in a video-mediated collaborative task. [Citation Graph (0, 0)][DBLP]
    CSCW, 2006, pp:403-412 [Conf]
  5. Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
    Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:741-746 [Conf]
  6. Amlan Ghosh, Abhishek Ranjan, Nirmal B. Chakrabarti
    Design and Implementation of Analog Multitone Signal Generator Using Regenerative Frequency Divider for OFDM Transceiver. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:23-30 [Conf]
  7. Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
    Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:253- [Conf]
  8. Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
    Fast and accurate estimation of floorplans in logic/high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:95-100 [Conf]
  9. Abhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh
    Layout aware retiming. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:25-30 [Conf]
  10. Maogang Wang, Abhishek Ranjan, Salil Raje
    Multi-Million Gate FPGA Physical Design Challenges. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:891-899 [Conf]
  11. Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh
    Fast Hierarchical Floorplanning with Congestion and Timing Control. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:357-362 [Conf]
  12. Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh
    Innovate or perish: FPGA physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:148-155 [Conf]
  13. Shahzad Malik, Abhishek Ranjan, Ravin Balakrishnan
    Interacting with large displays from a distance with vision-tracked multi-finger gestural input. [Citation Graph (0, 0)][DBLP]
    UIST, 2005, pp:43-52 [Conf]
  14. Abhishek Ranjan, Kia Bazargan, S. Ogrenci, Majid Sarrafzadeh
    Fast floorplanning for effective prediction and construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:341-351 [Journal]

  15. Improving meeting capture by applying television production principles with audio and motion detection. [Citation Graph (, )][DBLP]


  16. An exploration of social requirements for exercise group formation. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002