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Author:
Majid Sarrafzadeh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh
    RPack: routability-driven packing for cluster-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:629-634 [Conf]
  2. Chunhong Chen, Majid Sarrafzadeh
    Power reduction by simultaneous voltage scaling and gate sizing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:333-338 [Conf]
  3. Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication in technology independent phase. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:577-582 [Conf]
  4. Maogang Wang, Sung Lim, Jason Cong, Majid Sarrafzadeh
    Multi-way partitioning using bi-partition heuristics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:667- [Conf]
  5. Maogang Wang, Majid Sarrafzadeh
    Modeling and minimization of routing congestion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:185-190 [Conf]
  6. Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh
    Instruction generation and regularity extraction for reconfigurable processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:262-269 [Conf]
  7. Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
    Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:635-640 [Conf]
  8. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Optimal integer delay budgeting on directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:920-925 [Conf]
  9. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    Creating and Exploiting Flexibility in Steiner Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:195-198 [Conf]
  10. Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
    Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:395-400 [Conf]
  11. De-Sheng Chen, Majid Sarrafzadeh
    An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:783-788 [Conf]
  12. Jun Dong Cho, Majid Sarrafzadeh
    A Nuffer Distribution Algorithm for High-Speed Clock Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:537-543 [Conf]
  13. Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh
    Memory Segmentation to Exploit Sleep Mode Operation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:36-41 [Conf]
  14. Elof Frank, Salil Raje, Majid Sarrafzadeh
    Constrained Register Allocation in Bus Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:170-175 [Conf]
  15. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
    New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:126-131 [Conf]
  16. Sivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh
    Over-the-Cell Channel Routing for High Performance Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:600-603 [Conf]
  17. Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
    Unification of Budgeting and Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:758-761 [Conf]
  18. Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh
    A Quick Safari Through the Reconfiguration Jungle. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:172-177 [Conf]
  19. Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh
    Potential-NRG: Placement with Incomplete Data. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:279-282 [Conf]
  20. Bo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh
    Over-the-Cell Routers for New Cell Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:604-607 [Conf]
  21. Chunhong Chen, Majid Sarrafzadeh
    Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1016-1020 [Conf]
  22. Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh
    Layout driven data communication optimization for high level synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1185-1190 [Conf]
  23. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Incremental Timing Budget Management in Programmable Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:240-246 [Conf]
  24. Soheil Ghiasi, Hyun J. Moon, Majid Sarrafzadeh
    Collaborative and Reconfigurable Object Tracking. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:13-20 [Conf]
  25. Jun Dong Cho, Salil Raje, Majid Sarrafzadeh
    Approximation Algorithm on Multi-Way Maxcut Partitioning. [Citation Graph (0, 0)][DBLP]
    ESA, 1994, pp:148-158 [Conf]
  26. Soheil Ghiasi, Hyun J. Moon, Majid Sarrafzadeh
    Improving Performance and Quality thru Hardware Reconfiguration: Potentials and Adaptive Object Tracking Case Study. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:149-155 [Conf]
  27. Kiarash Barzagan, Majid Sarrafzadeh
    Fast Online Placement for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:300-0 [Conf]
  28. Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh
    A C to Hardware/Software Compiler. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:331-332 [Conf]
  29. Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Customized regular channel design in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:240- [Conf]
  30. Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    On computation and resource management in an FPGA-based computation environment. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:243- [Conf]
  31. F. S. Ogrenci, Aggelos K. Katsaggelos, Majid Sarrafzadeh
    FPGA implementation and analysis of image restoration. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:219- [Conf]
  32. Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh
    Routing algorithms: enhancing routability & enabling ECO (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:266- [Conf]
  33. Amir H. Farrahi, Majid Sarrafzadeh
    FPGA Technology Mapping for Power Minimization. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:66-77 [Conf]
  34. Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
    Fast and accurate estimation of floorplans in logic/high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:95-100 [Conf]
  35. Jim E. Crenshaw, Majid Sarrafzadeh
    Low Power Driven Scheduling and Binding. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:406-413 [Conf]
  36. Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran
    An Incremental Floorplanner. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:248-251 [Conf]
  37. Abhishek Ranjan, Ankur Srivastava, V. Karnam, Majid Sarrafzadeh
    Layout aware retiming. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:25-30 [Conf]
  38. Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh
    Block placement to ensure channel routability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:465-468 [Conf]
  39. De-Sheng Chen, Majid Sarrafzadeh
    A wire-length minimization algorithm for single-layer layouts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:390-393 [Conf]
  40. Chunhong Chen, Majid Sarrafzadeh
    Provably good algorithm for low power consumption with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:76-79 [Conf]
  41. Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Potential Slack: An Effective Metric of Combinational Circuit Performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:198-201 [Conf]
  42. Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh
    Incremental CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:236-243 [Conf]
  43. Morgan Enos, Scott Hauck, Majid Sarrafzadeh
    Replication for logic bipartitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:342-349 [Conf]
  44. Amir H. Farrahi, Majid Sarrafzadeh
    System partitioning to maximize sleep time. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:452-455 [Conf]
  45. Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh
    A unified theory of timing budget management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:653-659 [Conf]
  46. Jan-Ming Ho, Majid Sarrafzadeh, Atsushi Suzuki
    An Exact Algorithm for Single-Layer Wire-Length Minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:424-427 [Conf]
  47. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
    Algorithms for Three-Layer Over-The-Cell Channel Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:428-431 [Conf]
  48. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Predictable Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:110-113 [Conf]
  49. Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Instruction Generation for Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:127-0 [Conf]
  50. Wei-Liang Lin, Majid Sarrafzadeh, Chak-Kuen Wong
    The reproducing placement problem with applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:686-689 [Conf]
  51. Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    A Super-Scheduler for Embedded Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:391-0 [Conf]
  52. Malgorzata Marek-Sadowska, Majid Sarrafzadeh
    The Crossing Distribution Problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:528-531 [Conf]
  53. Majid Sarrafzadeh
    Transforming an arbitrary floorplan into a sliceable one. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:386-389 [Conf]
  54. Majid Sarrafzadeh, Maogang Wang
    NRG: global and detailed placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:532-537 [Conf]
  55. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
    Timing Driven Gate Duplication: Complexity Issues and Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:447-450 [Conf]
  56. Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
    Achieving Design Closure Through Delay Relaxation Parameter. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:54-57 [Conf]
  57. Ankur Srivastava, Majid Sarrafzadeh
    Predictability: definition, ananlysis and optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:118-121 [Conf]
  58. Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh
    Activity-driven clock design for low power circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:62-65 [Conf]
  59. Gustavo E. Téllez, Majid Sarrafzadeh
    Clock period constrained minimal buffer insertion in clock trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:219-223 [Conf]
  60. Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
    Timing-driven placement using design hierarchy guided constraint generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:177-180 [Conf]
  61. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion Reduction During Placement Based on Integer Programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:573-576 [Conf]
  62. Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh
    DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:260-263 [Conf]
  63. Huaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarrafzadeh
    A Trade-off Oriented Placement Tool. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:467-471 [Conf]
  64. Chunhong Chen, Majid Sarrafzadeh
    An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:222-0 [Conf]
  65. Bo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh
    Flow-Based Cell Moving Algorithm for Desired Cell Distribution. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:218-0 [Conf]
  66. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong
    Performance-Driven Global Routing for Cell Based ICs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:170-173 [Conf]
  67. Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh
    Fast Hierarchical Floorplanning with Congestion and Timing Control. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:357-362 [Conf]
  68. Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
    A Standard-Cell Placement Tool for Designs with High Row Utilization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:45-0 [Conf]
  69. Manbir Nag, Majid Sarrafzadeh
    A Parallel Algorithm for Two-Layer Wirin. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:278-285 [Conf]
  70. Ani Nahapetian, Foad Dabiri, Majid Sarrafzadeh
    Energy Minimization and Reliability for Wearable Medical Applications. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2006, pp:309-318 [Conf]
  71. Roozbeh Jafari, Seda Ogrenci Memik, Majid Sarrafzadeh
    Quick Reconfiguration in Clustered Micro-Sequencer. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  72. D. T. Lee, Majid Sarrafzadeh
    Maximum Independent Set of a Permutation Graph in k Tracks. [Citation Graph (0, 0)][DBLP]
    ISA, 1991, pp:2-11 [Conf]
  73. Majid Sarrafzadeh, D. T. Lee
    Rstricted Track Assignment with Applications. [Citation Graph (0, 0)][DBLP]
    ISAAC, 1992, pp:449-458 [Conf]
  74. Majid Sarrafzadeh, Dorothea Wagner, Frank Wagner, Karsten Weihe
    Wiring Knock-Knee Layouts: A Global Appoach. [Citation Graph (0, 0)][DBLP]
    ISAAC, 1992, pp:388-399 [Conf]
  75. Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
    Minimum Density Interconneciton Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1865-1868 [Conf]
  76. De-Sheng Chen, Majid Sarrafzadeh, Gary K. H. Yeap
    State Encoding of Finite State Machines for Low Power Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2309-2312 [Conf]
  77. Bo-Kyung Choi, Charles Chiang, Jamil Kawa, Majid Sarrafzadeh
    Routing resources consumption on M-arch and X-arch. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:73-76 [Conf]
  78. Wei-Liang Lin, Majid Sarrafzadeh
    A Linear Arrangement Problem with Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:57-60 [Conf]
  79. Salil Raje, Majid Sarrafzadeh
    GEM: A Geometric Algorithm for Scheduling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1991-1994 [Conf]
  80. Gustavo E. Téllez, Majid Sarrafzadeh
    On Rectilinear Distance-Preserving Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:163-166 [Conf]
  81. Majid Sarrafzadeh, Salil Raje
    Scheduling with multiple voltages under resource constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:350-353 [Conf]
  82. M. Sarrafzadeh, T. Takahashi
    A fast algorithm for routability testing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:178-181 [Conf]
  83. Chunhong Chen, Changjun Kang, Majid Sarrafzadeh
    Activity-sensitive clock tree construction for low power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:279-282 [Conf]
  84. Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh
    Early evaluation techniques for low power binding. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:160-165 [Conf]
  85. Salil Raje, Majid Sarrafzadeh
    Variable voltage scheduling. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:9-14 [Conf]
  86. Majid Sarrafzadeh, Foad Dabiri, Roozbeh Jafari, Tammara Massey, Ani Nahapetian
    Low power light-weight embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:207-212 [Conf]
  87. Jason Cong, Majid Sarrafzadeh
    Incremental physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:84-92 [Conf]
  88. Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
    Nostradamus: a floorplanner of uncertain design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:18-23 [Conf]
  89. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    An exact algorithm for coupling-free routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:10-15 [Conf]
  90. Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
    Design and analysis of physical design algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:82-89 [Conf]
  91. Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh
    Differences in ASIC, COT and processor design (panel). [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:2- [Conf]
  92. Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh
    Innovate or perish: FPGA physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:148-155 [Conf]
  93. Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh
    Dragon2006: blockage-aware congestion-controlling mixed-size placer. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:209-211 [Conf]
  94. Maogang Wang, Majid Sarrafzadeh
    On the behavior of congestion minimization during placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:145-150 [Conf]
  95. Maogang Wang, Xiaojian Yang, Kenneth Eguro, Majid Sarrafzadeh
    Multi-center congestion estimation and minimization during placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:147-152 [Conf]
  96. Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
    Routability driven white space allocation for fixed-die standard-cell placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:42-47 [Conf]
  97. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion estimation during top-down placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:164-169 [Conf]
  98. Xiaojian Yang, Maogang Wang, Kenneth Eguro, Majid Sarrafzadeh
    A snap-on placement tool. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:153-158 [Conf]
  99. Amir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh
    Quality of EDA CAD Tools: Definitions, Metrics and Directions. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:395-406 [Conf]
  100. Eren Kursun, Soheil Ghiasi, Majid Sarrafzadeh
    Transistor Level Budgeting for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:116-121 [Conf]
  101. Foad Dabiri, Roozbeh Jafari, Ani Nahapetian, Majid Sarrafzadeh
    A Unified Optimal Voltage Selection Methodology for Low-Power Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:210-218 [Conf]
  102. Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
    System Level Estimation of Interconnect Length in the Presence of IP Blocks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:438-443 [Conf]
  103. Taraneh Taghavi, Majid Sarrafzadeh
    Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:213-218 [Conf]
  104. Ankur Srivastava, Majid Sarrafzadeh
    Predictability: Definition, Analysis and Optimization. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:267-272 [Conf]
  105. Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid Sarrafzadeh
    A dictionary construction technique for code compression systems with echo instructions. [Citation Graph (0, 0)][DBLP]
    LCTES, 2005, pp:105-114 [Conf]
  106. Roozbeh Jafari, Andre Encarnacao, Azad Zahoory, Foad Dabiri, Hyduke Noshadi, Majid Sarrafzadeh
    Wireless Sensor Networks for Health Monitoring. [Citation Graph (0, 0)][DBLP]
    MobiQuitous, 2005, pp:479-781 [Conf]
  107. Roozbeh Jafari, Hyduke Noshadi, Majid Sarrafzadeh, Soheil Ghiasi
    Adaptive Medical Feature Extraction for Resource Constrained Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PerCom Workshops, 2006, pp:506-511 [Conf]
  108. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
    3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:38-0 [Conf]
  109. Roozbeh Jafari, Foad Dabiri, Majid Sarrafzadeh
    An Efficient Placement and Routing Technique for Fault-Tolerant Distributed Embedded Computing. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:135-143 [Conf]
  110. Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh
    Adaptive and fault tolerant medical vest for life-critical medical monitoring. [Citation Graph (0, 0)][DBLP]
    SAC, 2005, pp:272-279 [Conf]
  111. Roozbeh Jafari, Foad Dabiri, Bo-Kyung Choi, Majid Sarrafzadeh
    Efficient placement and routing in grid-based networks. [Citation Graph (0, 0)][DBLP]
    SAC, 2005, pp:899-900 [Conf]
  112. Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh
    Instruction Selection for Compilers that Target Architectures with Echo Instructions. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:229-243 [Conf]
  113. Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Wirelength estimation based on rent exponents of partitioning and placement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:25-31 [Conf]
  114. Ruey-Der Lou, Majid Sarrafzadeh, D. T. Lee
    An Optimal Algorithm for the Maximum Two-Chain Problem. [Citation Graph (0, 0)][DBLP]
    SODA, 1990, pp:149-158 [Conf]
  115. Gianfranco Bilardi, Scot W. Hornick, Majid Sarrafzadeh
    Optimal VLSI Architectures for Multidimensional DFT. [Citation Graph (0, 0)][DBLP]
    SPAA, 1989, pp:265-272 [Conf]
  116. Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh
    Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:423-427 [Conf]
  117. Sumit Roy, Prithviraj Banerjee, Majid Sarrafzadeh
    Partitioning sequential circuits for low power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:212-217 [Conf]
  118. Ryan Kastner, Christina Hsieh, Miodrag Potkonjak, Majid Sarrafzadeh
    On the Sensitivity of Incremental Algorithms for Combinatorial Auctions. [Citation Graph (0, 0)][DBLP]
    WECWIS, 2002, pp:81-88 [Conf]
  119. Yoji Kajitani, Jun Dong Cho, Majid Sarrafzadeh
    New Approximation Results on Graph Matching and related Problems. [Citation Graph (0, 0)][DBLP]
    WG, 1994, pp:343-358 [Conf]
  120. Kuo-Feng Liao, Majid Sarrafzadeh
    Vertex-Disjoint Trees and Boundary Single-Layer Routing. [Citation Graph (0, 0)][DBLP]
    WG, 1990, pp:99-108 [Conf]
  121. Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
    Budget Management with Applications. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 2002, v:34, n:3, pp:261-275 [Journal]
  122. Amir H. Farrahi, D. T. Lee, Majid Sarrafzadeh
    Two-Way and Multiway Partitioning of a Set of Intervals for Clique-Width Maximization. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1999, v:23, n:3, pp:187-210 [Journal]
  123. Scot W. Hornick, Majid Sarrafzadeh
    On Problem Transformability in VLSI. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1987, v:2, n:, pp:97-111 [Journal]
  124. Kurt Mehlhorn, Franco P. Preparata, Majid Sarrafzadeh
    Channel Routing in Knock-Knee Mode: Simplified Algorithms and Proofs. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1986, v:1, n:2, pp:213-221 [Journal]
  125. S. Nicoloso, Majid Sarrafzadeh, X. Song
    On the Sum Coloring Problem on Interval Graphs. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1999, v:23, n:2, pp:109-126 [Journal]
  126. Yachyang Sun, Majid Sarrafzadeh
    Floorplanning by Graph Dualization: L-shaped Modules. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1993, v:10, n:6, pp:429-456 [Journal]
  127. Majid Sarrafzadeh, Ruey-Der Lou
    Maximum k-Covering of Weighted Transitive Graphs with Applications. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1993, v:9, n:1, pp:84-100 [Journal]
  128. Ruey-Der Lou, Majid Sarrafzadeh
    Circular Permutation Graph Family with Applications. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1992, v:40, n:4, pp:433-457 [Journal]
  129. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
    Fast Template Placement for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:68-83 [Journal]
  130. Jun Dong Cho, Majid Sarrafzadeh, Mysore Sriram, Sung-Mo Kang
    High-Performance MCM Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:27-37 [Journal]
  131. D. T. Lee, Majid Sarrafzadeh
    Maximum independent set of a permutation graph in K tracks. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Geometry Appl., 1993, v:3, n:3, pp:291-304 [Journal]
  132. Majid Sarrafzadeh, D. T. Lee
    Restricted track assignment with applications. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Geometry Appl., 1994, v:4, n:1, pp:53-68 [Journal]
  133. Salil Raje, Majid Sarrafzadeh
    Scheduling with multiple voltages. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:23, n:1, pp:37-59 [Journal]
  134. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh
    Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:1, pp:77-100 [Journal]
  135. Ankur Srivastava, Eren Kursun, Majid Sarrafzadeh
    Predictability in RT-Level Designs. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:4, pp:323-332 [Journal]
  136. Jun Dong Cho, Majid Sarrafzadeh
    The pin redistribution problem in multi-chip modules. [Citation Graph (0, 0)][DBLP]
    Math. Program., 1994, v:63, n:, pp:297-330 [Journal]
  137. Ruey-Der Lou, Majid Sarrafzadeh, Chong S. Rim, Kazuo Nakajima, Sumio Masuda
    General Circular Permutation Layout. [Citation Graph (0, 0)][DBLP]
    Mathematical Systems Theory, 1992, v:25, n:4, pp:269-292 [Journal]
  138. D. T. Lee, Majid Sarrafzadeh, Ying-Fung Wu
    Minimum Cuts for Circular-Arc Graphs. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1990, v:19, n:6, pp:1041-1050 [Journal]
  139. Wei-Liang Lin, Amir H. Farrahi, Majid Sarrafzadeh
    On the Power of Logic Resynthesis. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 2000, v:29, n:4, pp:1257-1289 [Journal]
  140. Ruey-Der Lou, Majid Sarrafzadeh
    An Optimal Algorithm for the Maximum Three-Chain Problem. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1993, v:22, n:5, pp:976-993 [Journal]
  141. Kok-Hoo Yeap, Majid Sarrafzadeh
    Floor-Planning by Graph Dualization: 2-Concave Rectilinear Modules. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1993, v:22, n:3, pp:500-526 [Journal]
  142. Ruey-Der Lou, Majid Sarrafzadeh, D. T. Lee
    An Optimal Algorithm for the Maximum Two-Chain Problem. [Citation Graph (0, 0)][DBLP]
    SIAM J. Discrete Math., 1992, v:5, n:2, pp:285-304 [Journal]
  143. Gary K. H. Yeap, Majid Sarrafzadeh
    Sliceable Floorplanning by Graph Dualization. [Citation Graph (0, 0)][DBLP]
    SIAM J. Discrete Math., 1995, v:8, n:2, pp:258-280 [Journal]
  144. Martin L. Brady, Majid Sarrafzadeh
    Stretching a Knock-Knee Layout for Multilayer Wiring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:1, pp:148-151 [Journal]
  145. Jun Dong Cho, Salil Raje, Majid Sarrafzadeh
    Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering vor VLSI Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1253-1266 [Journal]
  146. Seda Ogrenci Memik, Aggelos K. Katsaggelos, Majid Sarrafzadeh
    Analysis and FPGA Implementation of Image Restoration under Resource Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:390-399 [Journal]
  147. Majid Sarrafzadeh
    Area Minimization in a Three-Sided Switchbox by Sliding the Modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:11, pp:1395-1403 [Journal]
  148. Majid Sarrafzadeh, D. T. Lee
    Topological Via Minimization Revisited. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:11, pp:1307-1312 [Journal]
  149. Majid Sarrafzadeh, Wei-Liang Lin, C. K. Wong
    Floating Steiner Trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:2, pp:197-211 [Journal]
  150. Majid Sarrafzadeh, C. K. Wong
    Bottleneck Steiner Trees in the Plane. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:3, pp:370-374 [Journal]
  151. Majid Sarrafzadeh, Dorothea Wagner, Frank Wagner, Karsten Weihe
    Wiring Knock-Knee Layouts: A Global Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:5, pp:581-589 [Journal]
  152. Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
    Nostradamus: a floorplanner of uncertain designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:389-397 [Journal]
  153. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Optimal integer delay-budget assignment on directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1184-1199 [Journal]
  154. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    Creating and exploiting flexibility in rectilinear Steiner trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:605-615 [Journal]
  155. Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi
    Fundamental CAD algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1449-1475 [Journal]
  156. Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh
    Optimal register sharing for high-level synthesis of SSA form programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:772-779 [Journal]
  157. Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Predicting potential performance for digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:253-262 [Journal]
  158. Charles Chiang, Majid Sarrafzadeh, Chak-Kuen Wong
    Global routing based on Steiner min-max trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1318-1325 [Journal]
  159. Charles Chiang, Chak-Kuen Wong, Majid Sarrafzadeh
    A weighted Steiner tree-based global router with simultaneous length and density minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1461-1469 [Journal]
  160. Jun Dong Cho, Majid Sarrafzadeh
    Four-bend top-down global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:793-802 [Journal]
  161. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong
    Provably good performance-driven global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:739-752 [Journal]
  162. Morgan Enos, Scott Hauck, Majid Sarrafzadeh
    Evaluation and optimization of replication algorithms for logic bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1237-1248 [Journal]
  163. Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
    Activity-driven clock design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:705-714 [Journal]
  164. Amir H. Farrahi, Majid Sarrafzadeh
    Complexity of the lookup-table minimization problem for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:11, pp:1319-1332 [Journal]
  165. Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh
    A Unified Theory of Timing Budget Management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2364-2375 [Journal]
  166. Jan-Ming Ho, Atsushi Suzuki, Majid Sarrafzadeh
    An exact algorithm for single-layer wire length minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:175-180 [Journal]
  167. Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
    Pad minimization for planar routing of multiple power nets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:419-426 [Journal]
  168. Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
    Layer assignment for multichip modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1272-1277 [Journal]
  169. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
    Utilization of vacant terminals for improved over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:780-792 [Journal]
  170. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Pattern routing: use and theory for increasing predictability andavoiding coupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:777-790 [Journal]
  171. Andrew B. Kahng, Majid Sarrafzadeh
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:1-2 [Journal]
  172. Kuo-Feng Liao, Majid Sarrafzadeh
    Boundary single-layer routing with movable terminals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1382-1391 [Journal]
  173. Kuo-Feng Liao, Majid Sarrafzadeh
    Correction to "Boundary single-layer routing with movable terminals". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:638- [Journal]
  174. Malgorzata Marek-Sadowska, Majid Sarrafzadeh
    The crossing distribution problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:423-433 [Journal]
  175. Majid Sarrafzadeh
    Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:503-506 [Journal]
  176. Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
    A delay budgeting algorithm ensuring maximum flexibility in placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1332-1341 [Journal]
  177. Majid Sarrafzadeh, D. T. Lee
    A new approach to topological via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:890-900 [Journal]
  178. Majid Sarrafzadeh, Kuo-Feng Liao, Chak-Kuen Wong
    Single-layer global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:38-47 [Journal]
  179. Majid Sarrafzadeh, Chak-Kuen Wong
    Hierarchical Steiner tree construction in uniform orientations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1095-1103 [Journal]
  180. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh
    On the complexity of gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1170-1176 [Journal]
  181. Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
    On effective slack management in postscheduling phase. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:645-653 [Journal]
  182. Gustavo E. Téllez, Majid Sarrafzadeh
    Minimal buffer insertion in clock trees with skew and slew rate constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:4, pp:333-342 [Journal]
  183. Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh
    Congestion minimization during placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1140-1148 [Journal]
  184. Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
    Routability-driven white space allocation for fixed-die standard-cell placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:410-419 [Journal]
  185. Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh
    Congestion estimation during top-down placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:72-80 [Journal]
  186. Gary K. H. Yeap, Majid Sarrafzadeh
    A unified approach to floorplan sizing and enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1858-1867 [Journal]
  187. Majid Sarrafzadeh, Sanjeev R. Maddila
    Discrete Warehouse Problem. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1995, v:140, n:2, pp:231-247 [Journal]
  188. Soheil Ghiasi, Ani Nahapetian, Majid Sarrafzadeh
    An optimal algorithm for minimizing run-time reconfiguration delay. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:237-256 [Journal]
  189. Soheil Ghiasi, Hyun J. Moon, Ani Nahapetian, Majid Sarrafzadeh
    Collaborative and Reconfigurable Object Tracking. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2004, v:30, n:3, pp:213-238 [Journal]
  190. Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    A scheduling algorithm for optimization and early planning in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:33-57 [Journal]
  191. Majid Sarrafzadeh, Rajeev Jayaraman
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:499-500 [Journal]
  192. Xiaojian Yang, Maogang Wang, Ryan Kastner, Soheil Ghiasi, Majid Sarrafzadeh
    Congestion reduction during placement with provably good approximation bound. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:3, pp:316-333 [Journal]
  193. Roozbeh Jafari, Hyduke Noshadi, Soheil Ghiasi, Majid Sarrafzadeh
    Adaptive Electrocardiogram Feature Extraction on Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:8, pp:797-807 [Journal]
  194. Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
    Timing driven gate duplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:42-51 [Journal]
  195. Ani Nahapetian, Paolo Lombardo, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh
    Dynamic reconfiguration in sensor networks with regenerative energy sources. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1054-1059 [Conf]
  196. Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh
    Routing algorithms: architecture driven rerouting enhancement for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  197. Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh
    Soft Error-Aware Power Optimization Using Gate Sizing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:255-267 [Conf]
  198. Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Majid Sarrafzadeh
    Optimization for Real-Time Systems with Non-convex Power Versus Speed Models. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:443-452 [Conf]
  199. Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh
    Tutorial on congestion prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:15-24 [Conf]
  200. Roozbeh Jafari, Soheil Ghiasi, Majid Sarrafzadeh
    Medical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:441-444 [Conf]
  201. Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh
    On gate level power optimization using dual-supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:616-629 [Journal]
  202. Abhishek Ranjan, Kia Bazargan, S. Ogrenci, Majid Sarrafzadeh
    Fast floorplanning for effective prediction and construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:341-351 [Journal]
  203. Roozbeh Jafari, Foad Dabiri, Majid Sarrafzadeh
    Epsilon-Optimal Minimal-Skew Battery Lifetime Routing in Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:97-107 [Journal]
  204. Soheil Ghiasi, Elaheh Bozorgzadeh, Karlene Nguyen, Majid Sarrafzadeh
    Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:1, pp:43-55 [Journal]

  205. Accelerating total variation regularization for matrix-valued images on GPUs. [Citation Graph (, )][DBLP]


  206. Accurate high level datapath power estimation. [Citation Graph (, )][DBLP]


  207. Energy minimization for real-time systems with non-convex and discrete operation modes. [Citation Graph (, )][DBLP]


  208. Scalable medium access control for in-network data aggregation. [Citation Graph (, )][DBLP]


  209. Fast GPU-based space-time correlation for activity recognition in video sequences. [Citation Graph (, )][DBLP]


  210. Communication bottleneck in hardware-software partitioning. [Citation Graph (, )][DBLP]


  211. Toward Unsupervised Activity Discovery Using Multi-Dimensional Motif Detection in Time Series. [Citation Graph (, )][DBLP]


  212. Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  213. Power aware placement for FPGAs with dual supply voltages. [Citation Graph (, )][DBLP]


  214. Participatory user centered design techniques for a large scale ad-hoc health information system. [Citation Graph (, )][DBLP]


  215. HERO: Hybrid Emergency Route-Opening Protocol. [Citation Graph (, )][DBLP]


  216. HIP: Health integration platform. [Citation Graph (, )][DBLP]


  217. Interference graphs for procedures in static single information form are interval graphs. [Citation Graph (, )][DBLP]


  218. Unsupervised Discovery of Abnormal Activity Occurrences in Multi-dimensional Time Series, with Applications in Wearable Systems. [Citation Graph (, )][DBLP]


  219. Theoretical Bound and Practical Analysis of Connected Dominating Set in Ad Hoc and Sensor Networks. [Citation Graph (, )][DBLP]


  220. Opportunistic medical monitoring using bluetooth P2P networks. [Citation Graph (, )][DBLP]


  221. Optimizing Interval Training Protocols Using Data Mining Decision Trees. [Citation Graph (, )][DBLP]


  222. Remote Medical Monitoring Through Vehicular Ad Hoc Network. [Citation Graph (, )][DBLP]


  223. Interval training guidance system with music and wireless group exercise motivations. [Citation Graph (, )][DBLP]


  224. A Wireless Embedded Device for Personalized Ultraviolet Monitoring. [Citation Graph (, )][DBLP]


  225. Linear frequency estimation technique for reducing frequency based signals. [Citation Graph (, )][DBLP]


  226. A memory optimization technique for software-managed scratchpad memory in GPUs. [Citation Graph (, )][DBLP]


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