Conferences in DBLP
Lin Li , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin Adapative Error Protection for Energy Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Ruibing Lu , Cheng-Kok Koh SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Hongyu Chen , Chung-Kuan Cheng , Andrew B. Kahng , Ion I. Mandoiu , Qinke Wang , Bo Yao The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Vishnu Swaminathan , Krishnendu Chakrabarty Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoxiong Hua , Gang Qu Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Le Yan , Jiong Luo , Niraj K. Jha Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Wang , Sumit Roy RTL Power Optimization with Gate-Level Accuracy. [Citation Graph (0, 0)][DBLP ] Conf ] Chao Huang , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Srivastava , Seda Ogrenci Memik , Bo-Kyung Choi , Majid Sarrafzadeh Achieving Design Closure Through Delay Relaxation Parameter. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Swahn , Soha Hassoun Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , Xiaoping Tang , Martin D. F. Wong Bus-Driven Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Peter G. Sassone , Sung Kyu Lim A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Cristinel Ababei , Kia Bazargan Placement Method Targeting Predictability Robustness and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Brent Goplen , Sachin S. Sapatnekar Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Partial Core Encryption for Performance-Efficient Test of SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Anuja Sehgal , Sule Ozev , Krishnendu Chakrabarty TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Xia , Malgorzata Chrzanowska-Jeske , Benyi Wang , Marcin Jeske Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto García Ortiz , Lukusa D. Kabulepa , Tudor Murgan , Manfred Glesner Moment-Based Power Estimation in Very Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mamidipaka , Kamal S. Khouri , Nikil D. Dutt , Magdy S. Abadir IDAP: A Tool for High Level Power Estimation of Custom Array Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Kerry Bernstein , Ching-Te Chuang , Rajiv V. Joshi , Ruchir Puri Design and CAD Challenges in sub-90nm CMOS Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] In-Cheol Park , Sehyeon Kang , Yongseok Yi Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yuan , Carl Pixley , Adnan Aziz , Ken Albin A Framework for Constrained Functional Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Yunshan Zhu , James H. Kukula Generator-based Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Alan J. Hu , Jeremy Casas , Jin Yang Efficient Generation of Monitor Circuits for GSTE Assertion Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail Weibull Based Analytical Waveform Model. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Hashimoto , Yuji Yamada , Hidetoshi Onodera Equivalent Waveform Propagation for Static Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Rubil Ahmadi , Farid N. Najm Timing Analysis in Presence of Power Supply and Ground Voltage Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Pant , David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda Vectorless Analysis of Supply Noise Induced Delay Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Guilin Chen , Mahmut T. Kandemir , A. Nadgir , Ugur Sezer Array Composition and Decomposition for Optimizing Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Junhyung Um , Taewhan Kim Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jinfeng Liu , Pai H. Chou Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Zhang , Krishnendu Chakrabarty , Vishnu Swaminathan Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan Lin , Hai Zhou Retiming for Wire Pipelining in System-On-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Chris C. N. Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu Retiming with Interconnect and Gate Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Ruibing Lu , Cheng-Kok Koh Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Held , Bernhard Korte , Jens Maßberg , Matthias Ringe , Jens Vygen Clock Scheduling and Clocktree Construction for High Performance ASICS. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Stehr , Michael Pronath , Frank Schenkel , Helmut E. Graeb , Kurt Antreich Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Piet Vanassche , Georges G. E. Gielen , Willy M. C. Sansen A Generalized Method for Computing Oscillator Phase Noise Spectra. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrice Veersé Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitri Maslov , Gerhard W. Dueck , D. Michael Miller Fredkin/Toffoli Templates for Reversible Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Ion I. Mandoiu , Sherief Reda , Xu Xu , Alexander Zelikovsky Evaluation of Placement Techniques for DNA Probe Array Layout. [Citation Graph (0, 0)][DBLP ] Conf ] S. K. De , Narayan R. Aluru Physical And Reduced-Order Dynamic Analysis of MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Claire Fang Fang , Rob A. Rutenbar , Tsuhan Chen Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Sun , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha A Scalable Application-Specific Processor Synthesis Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Newton Cheung , Sri Parameswaran , Jörg Henkel INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tony F. Chan , Jason Cong , Tim Kong , Joseph R. Shinnerl , Kenton Sze An Enhanced Multilevel Algorithm for Circuit Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Ameya R. Agnihotri , Mehmet Can Yildiz , Ateen Khatkhate , Ajita Mathur , Satoshi Ono , Patrick H. Madden Fractional Cut: Improved Recursive Bisection Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh N. Adya , Igor L. Markov , Paul Villarrubia On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Madhu K. Iyer , Ganapathy Parthasarathy , Kwang-Ting Cheng SATORI - A Fast Sequential SAT Engine for Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Cong Liu , Andreas Kuehlmann , Matthew W. Moskewicz CAMA: A Multi-Valued Satisfiability Solver. [Citation Graph (0, 0)][DBLP ] Conf ] Chao Wang , Gary D. Hachtel , Fabio Somenzi The Compositional Far Side of Image Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Arijit Ghosh , Tony Givargis Cache Optimization For Embedded Processor Cores: An Analytical Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu , Nicholas H. Zamora , Phillip Stanley-Marbell , Radu Marculescu Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rami Beidas , Jianwen Zhu Performance Efficiency of Context-Flow System-on-Chip Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Won Namgoong , Jongrit Lerdworatawee Amplification of Ultrawideband Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Taherzadeh-Sani , Reza Lotfi , Omid Shoaei A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Reza Lotfi , Mohammad Taherzadeh-Sani , M. Yaser Azizi , Omid Shoaei Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Dean Liu , Stefanos Sidiropoulos , Mark Horowitz A Framework for Designing Reusable Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Yi Ho , Yao-Wen Chang , Sao-Jie Chen , D. T. Lee A Fast Crosstalk- and Performance-Driven Multilevel Routing System. [Citation Graph (0, 0)][DBLP ] Conf ] Seokjin Lee , Yongseok Cheon , Martin D. F. Wong A Min-Cost Flow Based Detailed Router for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammet Mustafa Ozdal , Martin D. F. Wong Length-Matching Routing for High-Speed Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Rajaram , Bing Lu , Wei Guo , Rabi N. Mahapatra , Jiang Hu Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Chao Wang , Bing Li , HoonSang Jin , Gary D. Hachtel , Fabio Somenzi Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Malay K. Ganai , Zijiang Yang , Pranav Ashar Iterative Abstraction using SAT-based BMC with Proof Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Curtis A. Nelson , Chris J. Myers , Tomohiro Yoneda Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gérard Berry , Michael Kishinevsky , Satnam Singh System Level Design and Verification Using a Synchronous Language. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Demir Noise Analysis for Optical Fiber Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Joel R. Phillips , João Afonso , Arlindo L. Oliveira , Luis Miguel Silveira Analog Macromodeling using Kernel Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Li , Xin Li , Yang Xu , Lawrence T. Pileggi A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wonjoon Choi , Kia Bazargan Incremental Placement for Timing Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Huaiyu Xu , Maogang Wang , Bo-Kyung Choi , Majid Sarrafzadeh A Trade-off Oriented Placement Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Michail Romesis , Min Xie Optimality and Stability Study of Timing-Driven Placement Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] R. Iris Bahar , Joseph L. Mundy , Jie Chen A Probabilistic-Based Design Methodology for Nanoscale Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Arijit Raychowdhury , Saibal Mukhopadhyay , Kaushik Roy Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jiayong Le , Lawrence T. Pileggi , Anirudh Devgan Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Mahapatra , Kaustav Banerjee , Florent Pegeon , Adrian M. Ionescu A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Iranli , Hanif Fatemi , Massoud Pedram A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Girish Varatkar , Radu Marculescu Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Kalla , Xiaobo Sharon Hu , Jörg Henkel LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Alex Orailoglu Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiru Zhang , Yiping Fan , Miodrag Potkonjak , Jason Cong Gradual Relaxation Techniques with Applications to Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yiping Fan , Guoling Han , Xun Yang , Zhiru Zhang Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Ansgar Stammermann , Domenik Helms , Milan Schulte , Arne Schulz , Wolfgang Nebel Binding, Allocation and Floorplanning in Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pallav Gupta , Lin Zhong , Niraj K. Jha A High-level Interconnect Power Model for Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal Khandelwal , Azadeh Davoodi , Akash Nanavati , Ankur Srivastava A Probabilistic Approach to Buffer Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe S. Garcea , N. P. van der Meijs , Ralph H. J. M. Otten Simultaneous Analytic Area and Power Optimization for Repeater Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Weiping Liao , Lei He Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Ruiming Li , Dian Zhou , Jin Liu , Xuan Zeng Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis , Nadir Achouri , Slimane Boutobza Dynamic Data-bit Memory Built-In Self- Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Liang Cheng , Chih-Wea Wang , Jih-Nung Lee , Yung-Fa Chou , Chih-Tsun Huang , Cheng-Wen Wu FAME: A Fault-Pattern Based Memory Failure Analysis Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Bai Hong Fang , Qiang Xu , Nicola Nicolici Hardware/Software Co-testing of Embedded Memories in Complex SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan , Chandramouli V. Kashyap Block-based Static Timing Analysis with Uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw AU: Timing Analysis Under Uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] Hongliang Chang , Sachin S. Sapatnekar Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Kim , David Blaauw , Trevor N. Mudge Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip Stanley-Marbell , Diana Marculescu Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Sekar , Kanishka Lahiri , Sujit Dey Dynamic Platform Management for Configurable Platform-Based System-on-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Sheldon X.-D. Tan A General S-Domain Hierarchical Network Reduction Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard N. Sheehan Branch Merge Reduction of RLCM Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick L. Le Coz , Dhivya Krishna , Dusan M. Petranovic , William M. Loh , Peter Bendix A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Bozena Kaminska , Karim Arabi Mixed Signal DFT: A Concise Overview. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng Manufacturing-Aware Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul M. Rao , Frank Liu , Jeffrey L. Burns , Richard B. Brown A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Hsien-Hsin Sean Lee Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. [Citation Graph (0, 0)][DBLP ] Conf ] Julien Lamoureux , Steven J. E. Wilton On the Interaction Between Power-Aware FPGA CAD Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Robert K. Brayton A Theory of Non-Deterministic Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Yongseok Cheon , Seokjin Lee , Martin D. F. Wong Stable Multiway Circuit Partitioning for ECO. [Citation Graph (0, 0)][DBLP ] Conf ] Navaratnasothie Selvakkumaran , George Karypis Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhua Liu , Shuo Zhou , Haikun Zhu , Chung-Kuan Cheng An Algorithmic Approach for Generic Parallel Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Yang , C.-J. Richard Shi FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Abhishek Singh , Jitin Tharian , Jim Plusquellic Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Ion I. Mandoiu , Puneet Sharma Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Aman Kokrady , C. P. Ravikumar Static Verification of Test Vectors for IR Drop Failure. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Kundu , R. D. (Shawn) Blanton ATPG for Noise-Induced Switch Failures in Domino Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Imad A. Ferzli , Farid N. Najm Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandra Nardi , Haibo Zeng , Joshua L. Garrett , Luca Daniel , Alberto L. Sangiovanni-Vincentelli A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching Activity. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Hao Chen , Clement Luk , Charlie Chung-Ping Chen SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Zhao Li , C.-J. Richard Shi SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Ravindran , Andreas Kuehlmann , Ellen Sentovich Multi-Domain Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hsu Huang , Yow-Tyng Nieh Clock Period Minimization of Non-Zero Clock Skew Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Yang Yeh , Malgorzata Marek-Sadowska Minimum-Area Sequential Budgeting for FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Carmona , Jordi Cortadella ILP Models for the Synthesis of Asynchronous Control Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Traianos Yioultsis , Anne Woo , Andreas C. Cangellaris Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Pamunuwa , Shauki Elassaad , Hannu Tenhunen Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Song , Zhenhai Zhu , John D. Rockway , Jacob White A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Cao , Xiao-Dong Yang , Xuejue Huang , Dennis Sylvester Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Chen Wang , Sudhakar M. Reddy , Irith Pomeranz , Janusz Rajski , Jerzy Tyszer On Compacting Test Response Data Containing Unknown Values. [Citation Graph (0, 0)][DBLP ] Conf ] C. V. Krishna , Nur A. Touba Adjustable Width Linear Combinational Scan Vector Decompression. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Sandy Irani , Sandeep K. Shukla Formal Methods for Dynamic Power Management. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Tim Kong , Joseph R. Shinnerl , Min Xie , Xin Yuan Large-Scale Circuit Placement: Gap and Promise. [Citation Graph (0, 0)][DBLP ] Conf ] Maogang Wang , Abhishek Ranjan , Salil Raje Multi-Million Gate FPGA Physical Design Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Aseem Agarwal , David Blaauw , Vladimir Zolotov Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Ken-ichi Okada , Kento Yamaoka , Hidetoshi Onodera A Statistical Gate-Delay Model Considering Intra-Gate Variability. [Citation Graph (0, 0)][DBLP ] Conf ] Aseem Agarwal , David Blaauw , Vladimir Zolotov Statistical Clock Skew Analysis Considering Intra-Die Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] D. Nadezhin , Sergey Gavrilov , Alexey Glebov , Y. Egorov , Vladimir Zolotov , David Blaauw , Rajendran Panda , Murat R. Becer , A. Ardelea , A. Patel SOI Transistor Model for Fast Transient Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] 