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Kia Bazargan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
    Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:88-101 [Conf]
  2. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
    Three-dimensional place and route for FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:773-778 [Conf]
  3. Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
    Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:635-640 [Conf]
  4. Jinghuan Chen, Jaekyun Moon, Kia Bazargan
    A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:349-354 [Conf]
  5. Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
    Fast timing-driven partitioning-based placement for island style FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:598-603 [Conf]
  6. Cristinel Ababei, Kia Bazargan
    Statistical Timing Driven Partitioning for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1109- [Conf]
  7. Wonjoon Choi, Kia Bazargan
    Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11104-11105 [Conf]
  8. Karthikeyan Bhasyam, Kia Bazargan
    HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:264-271 [Conf]
  9. Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh
    A C to Hardware/Software Compiler. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:331-332 [Conf]
  10. Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan
    Linear Placement for Static / Dynamic Reconfiguration in JBits. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:300-301 [Conf]
  11. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
    3D FPGAs: placement, routing, and architecture evaluation (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:263- [Conf]
  12. Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh
    HARP: hard-wired routing pattern FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:21-29 [Conf]
  13. Satish Sivaswamy, Kia Bazargan
    Variation-aware routing for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:71-79 [Conf]
  14. Cristinel Ababei, Pongstorn Maidee, Kia Bazargan
    Exploring Potential Benefits of 3D FPGA Integration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:874-880 [Conf]
  15. Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
    Fast and accurate estimation of floorplans in logic/high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:95-100 [Conf]
  16. Cristinel Ababei, Kia Bazargan
    Placement Method Targeting Predictability Robustness and Performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:81-85 [Conf]
  17. Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis
    Multi-objective circuit partitioning for cutsize and path-based delay minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:181-185 [Conf]
  18. Wonjoon Choi, Kia Bazargan
    Incremental Placement for Timing Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:463-466 [Conf]
  19. Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh
    Fast Hierarchical Floorplanning with Congestion and Timing Control. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:357-362 [Conf]
  20. Cristinel Ababei, Kia Bazargan
    Non-Contiguous Linear Placement for Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  21. Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
    Nostradamus: a floorplanner of uncertain design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:18-23 [Conf]
  22. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
    3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:38-0 [Conf]
  23. Cristinel Ababei, Kia Bazargan
    Timing Minimization by Statistical Timing hMetis-based Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:58-63 [Conf]
  24. Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar
    Placement and Routing in 3D Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:520-531 [Journal]
  25. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
    Fast Template Placement for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:68-83 [Journal]
  26. Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
    A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:5, pp:596-606 [Journal]
  27. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
    Three-dimensional place and route for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1132-1140 [Journal]
  28. Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
    Nostradamus: a floorplanner of uncertain designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:389-397 [Journal]
  29. Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
    Timing-driven partitioning-based placement for island style FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:395-406 [Journal]
  30. Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
    Statistical Analysis and Design of HARP FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2088-2102 [Journal]
  31. John Lach, Kia Bazargan
    Editorial: Special issue on dynamically adaptable embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:233-236 [Journal]
  32. Hushrav Mogal, Kia Bazargan
    Microarchitecture floorplanning for sub-threshold leakage reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1238-1243 [Conf]
  33. Pongstorn Maidee, Kia Bazargan
    Defect-Tolerant FPGA Architecture Exploration. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  34. Abhishek Ranjan, Kia Bazargan, S. Ogrenci, Majid Sarrafzadeh
    Fast floorplanning for effective prediction and construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:341-351 [Journal]

  35. Using randomization to cope with circuit uncertainty. [Citation Graph (, )][DBLP]


  36. Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. [Citation Graph (, )][DBLP]


  37. A generalized and unified SPFD-based rewiring technique. [Citation Graph (, )][DBLP]


  38. FPGA family composition and effects of specialized blocks. [Citation Graph (, )][DBLP]


  39. A reconfigurable stochastic architecture for highly reliable computing. [Citation Graph (, )][DBLP]


  40. Clustering based pruning for statistical criticality computation under process variations. [Citation Graph (, )][DBLP]


  41. Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. [Citation Graph (, )][DBLP]


  42. The synthesis of combinational logic to generate probabilities. [Citation Graph (, )][DBLP]


  43. Estimation and optimization of reliability of noisy digital circuits. [Citation Graph (, )][DBLP]


  44. A tileable switch module architecture for homogeneous 3D FPGAs. [Citation Graph (, )][DBLP]


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