Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 2

1. Radu Marculescu, Diana Marculescu, Massoud Pedram
   Probabilistic modeling of dependencies during switching activity analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:73-83 [Journal]
   
2. James E. Beck, Daniel P. Siewiorek
   Automatic configuration of embedded multicomputer systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:84-95 [Journal]
   
3. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
   Incorporating DRAM access modes into high-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:96-109 [Journal]
   
4. Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El Gamal
   Optimizing dominant time constant in RC circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:110-125 [Journal]
   
5. Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
   A unified approach to topology generation and optimal sizing of floorplans. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:126-135 [Journal]
   
6. Kaiyuan Huang, Vinod K. Agarwal, Krishnaiyan Thulasiraman
   Diagnosis of clustered faults and wafer testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:136-148 [Journal]
   
7. Valery Axelrad
   Grid quality and its influence on accuracy and convergence in device simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:149-157 [Journal]
   
8. Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
   A controller redesign technique to enhance testability of controller-data path circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:157-168 [Journal]
   
9. Steve H. Jen, Bing J. Sheu
   A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:169-172 [Journal]
   
10. Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
    Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:173-182 [Journal]
    
11. Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen
    NEWS: a net-even-wiring system for the routing on a multilayer PGA package. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:182-189 [Journal]