Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 3

1. Miodrag Potkonjak, Jan M. Rabaey
   Optimizing resource utilization using transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:277-292 [Journal]
   
2. Philip B. M. Wolbert, Gerhard K. M. Wachutka, Benno H. Krabbenborg, Ton J. Mouthaan
   Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:293-302 [Journal]
   
3. Ting-Hai Chao, Yu-Chin Hsu
   Rectilinear Steiner tree construction by local and global refinement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:303-309 [Journal]
   
4. Ronald J. G. Goossens, Stephen G. Beebe, Zhiping Yu, Robert W. Dutton
   An automatic biasing scheme for tracing arbitrarily shaped I-V curves. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:310-317 [Journal]
   
5. Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu
   Timed Boolean calculus and its applications in timing analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:318-337 [Journal]
   
6. Peter M. Maurer, Yun Sik Lee
   Gateways: a technique for adding event-driven behavior to compiled simulations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:338-352 [Journal]
   
7. Bechir Ayari, Bozena Kaminska
   A new dynamic test vector compaction for automatic test pattern generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:353-358 [Journal]
   
8. Víctor H. Champac, Antonio Rubio, Joan Figueras
   Electrical model of the floating gate defect in CMOS ICs: implications on I_DDQ testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:359-369 [Journal]
   
9. Beyin Chen, Chung-Len Lee
   A complement-based fast algorithm to generate universal test sets for multi-output functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:370-377 [Journal]
   
10. Irith Pomeranz, Sudhakar M. Reddy
    On achieving complete fault coverage for sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:378-386 [Journal]
    
11. Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
    An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:387-395 [Journal]
    
12. Russell Kao, Mark Horowitz
    Eliminating redundant DC equations for asymptotic waveform evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:396-397 [Journal]