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Mark Horowitz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
    The Stanford FLASH Multiprocessor. [Citation Graph (2, 0)][DBLP]
    ISCA, 1994, pp:302-313 [Conf]
  2. Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
    An Evaluation of Directory Schemes for Cache Coherence. [Citation Graph (1, 0)][DBLP]
    ISCA, 1988, pp:280-289 [Conf]
  3. Anant Agarwal, John L. Hennessy, Mark Horowitz
    Cache Performance of Operating System and Multiprogramming Workloads. [Citation Graph (1, 0)][DBLP]
    ACM Trans. Comput. Syst., 1988, v:6, n:4, pp:393-431 [Journal]
  4. Anant Agarwal, Mark Horowitz, John L. Hennessy
    An Analytical Cache Model. [Citation Graph (1, 0)][DBLP]
    ACM Trans. Comput. Syst., 1989, v:7, n:2, pp:184-215 [Journal]
  5. Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz
    The Stream Virtual Machine. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:267-277 [Conf]
  6. David L. Harris, Stuart F. Oberman, Mark Horowitz
    SRT Division Architectures and Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:18-25 [Conf]
  7. H. Dhanesha, K. Falakshahi, Mark Horowitz
    Array-of-arrays architecture for parallel floating point multiplication. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:150-157 [Conf]
  8. Mark Heinrich, Jeffrey Kuskin, David Ofelt, John Heinlein, Joel Baxter, Jaswinder Pal Singh, Richard Simoni, Kourosh Gharachorloo, David Nakahira, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
    The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:274-285 [Conf]
  9. James Laudon, Anoop Gupta, Mark Horowitz
    Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:308-318 [Conf]
  10. Michael D. Smith, Mark Horowitz, Monica S. Lam
    Efficient Superscalar Performance Through Boosting. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:248-259 [Conf]
  11. Michael D. Smith, Mike Johnson, Mark Horowitz
    Limits on Multiple Instruction Issue. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:290-302 [Conf]
  12. David Lie, Chandramohan A. Thekkath, Mark Mitchell, Patrick Lincoln, Dan Boneh, John C. Mitchell, Mark Horowitz
    Architectural Support for Copy and Tamper Resistant Software. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:168-177 [Conf]
  13. Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Marc Levoy, Mark Horowitz
    High-Speed Videography Using a Dense Camera Array. [Citation Graph (0, 0)][DBLP]
    CVPR (2), 2004, pp:294-301 [Conf]
  14. Jules P. Bergmann, Mark Horowitz
    Vex - A CAD Toolbox. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:523-528 [Conf]
  15. C. W. Carpenter, Mark Horowitz
    Generating Incremental VLSI Compaction Spacing Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:291-297 [Conf]
  16. Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz
    Approximate Reachability with BDDs Using Overlapping Projections. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:451-456 [Conf]
  17. Hema Kapadia, Mark Horowitz
    Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:592-597 [Conf]
  18. Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong
    Design of a 10GHz clock distribution network using coupled standing-wave oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:682-687 [Conf]
  19. Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
    Reshaping EDA for power. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:15- [Conf]
  20. Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow
    Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:85- [Conf]
  21. A. Salz, Mark Horowitz
    IRSIM: An Incremental MOS Switch-Level Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:173-178 [Conf]
  22. Jeff Solomon, Mark Horowitz
    Using Texture Mapping with Mipmapping to Render a VLSI Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:500-505 [Conf]
  23. Don Stark, Mark Horowitz
    RED: Resistance Extraction for Digital Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:570-573 [Conf]
  24. Don Stark, Mark Horowitz
    Analyzing CMOS Power Supply Networks Using Ariel. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:460-464 [Conf]
  25. Jules P. Bergmann, Mark Horowitz
    Improving coverage analysis and test generation for large designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:580-583 [Conf]
  26. Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic
    Methods for true power minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:35-42 [Conf]
  27. Richard C. Ho, Mark Horowitz
    Validation coverage analysis for complex digital designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:146-151 [Conf]
  28. Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz
    Interconnect scaling implications for CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:425-429 [Conf]
  29. Russell Kao, Mark Horowitz
    Piecewise linear models for Rsim. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:753-758 [Conf]
  30. Dean Liu, Stefanos Sidiropoulos, Mark Horowitz
    A Framework for Designing Reusable Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:375-381 [Conf]
  31. Mark E. Dean, David L. Dill, Mark Horowitz
    Self-Timed Logic Using Current-Sensing Completion Detection (CSCD). [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:187-191 [Conf]
  32. Mark Horowitz
    High-Speed Link Design, Then and Now. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:- [Conf]
  33. Junji Ogawa, Mark Horowitz
    A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:1-14 [Conf]
  34. Anant Agarwal, Richard L. Sites, Mark Horowitz
    ATUM: A New Technique for Capturing Address Traces Using Microcode. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:119-127 [Conf]
  35. Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
    An Evaluation of Directory Schemes for Cache Coherence. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:353-362 [Conf]
  36. Paul Chow, Mark Horowitz
    Architectural Tradeoffs in the Design of MIPS-X. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:300-308 [Conf]
  37. Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill
    Architecture Validation for Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:404-413 [Conf]
  38. Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
    Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:260-270 [Conf]
  39. Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
    The Stanford FLASH Multiprocessor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:485-496 [Conf]
  40. Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
    Smart Memories: a modular reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:161-171 [Conf]
  41. Steven A. Przybylski, Mark Horowitz, John L. Hennessy
    Performance Tradeoffs in Cache Design. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:290-298 [Conf]
  42. Steven A. Przybylski, Mark Horowitz, John L. Hennessy
    Characteristics of Performance-Optimal Multi-Level Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:114-121 [Conf]
  43. Richard Simoni, Mark Horowitz
    Modeling the Performance of Limited Pointers Directories for Cache Coherence. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:309-319 [Conf]
  44. Michael D. Smith, Monica S. Lam, Mark Horowitz
    Boosting Beyond Static Scheduling in a Superscalar Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:344-354 [Conf]
  45. Dan Teodosiu, Joel Baxter, Kinshuk Govil, John Chapin, Mendel Rosenblum, Mark Horowitz
    Hardware Fault Containment in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:73-84 [Conf]
  46. Kimiyoshi Usami, Mark Horowitz
    Clustered voltage scaling technique for low-power design. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:3-8 [Conf]
  47. Gu-Yeon Wei, Mark Horowitz
    A low power switching power supply for self-clocked systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:313-317 [Conf]
  48. Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd
    A New Method for Design of Robust Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:676-681 [Conf]
  49. James A. Gasbarro, Mark Horowitz
    Techniques for Characterizing DRAMs With a 500-MHz Interface. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:516-525 [Conf]
  50. Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz
    Optimizing the Mapping of Low-Density Parity Check Codes on Parallel Decoding Architectures. [Citation Graph (0, 0)][DBLP]
    ITCC, 2001, pp:578-0 [Conf]
  51. Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, David Miller, Mark Horowitz, Olav Solgaard, Nick McKeown
    Scaling internet routers using optics. [Citation Graph (0, 0)][DBLP]
    SIGCOMM, 2003, pp:189-200 [Conf]
  52. David Lie, Chandramohan A. Thekkath, Mark Horowitz
    Implementing an untrusted operating system on trusted hardware. [Citation Graph (0, 0)][DBLP]
    SOSP, 2003, pp:178-192 [Conf]
  53. David Lie, John C. Mitchell, Chandramohan A. Thekkath, Mark Horowitz
    Specifying and Verifying Hardware for Tamper-Resistant Software. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Security and Privacy, 2003, pp:166-0 [Conf]
  54. Mark Horowitz
    Scaling, Power and the Future of CMOS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:23- [Conf]
  55. Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Wolf-Dietrich Weber, Anoop Gupta, John L. Hennessy, Mark Horowitz, Monica S. Lam
    The Stanford Dash Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:3, pp:63-79 [Journal]
  56. Nick McKeown, Martin Izzard, Adisak Mekkittikul, Bill Ellersick, Mark Horowitz
    The Tiny Tera: A Packet Switch Core [Citation Graph (0, 0)][DBLP]
    CoRR, 1998, v:0, n:, pp:- [Journal]
  57. Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz
    On task mapping optimization for parallel decoding of low-density parity-check codes on message-passing architectures. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2005, v:31, n:5, pp:462-490 [Journal]
  58. Chorng-Yeong Chu, Mark Horowitz
    Charge-Sharing Models for Switch-Level Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1053-1061 [Journal]
  59. David L. Harris, Mark Horowitz, Dean Liu
    Timing analysis including clock skew. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1608-1618 [Journal]
  60. Mark Horowitz, Robert W. Dutton
    Resistance Extraction from Mask Layout Data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:145-150 [Journal]
  61. Russell Kao, Mark Horowitz
    Eliminating redundant DC equations for asymptotic waveform evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:396-397 [Journal]
  62. Russell Kao, Mark Horowitz
    Timing analysis for piecewise linear Rsim. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1498-1512 [Journal]
  63. Don Stark, Mark Horowitz
    Techniques for calculating currents and voltages in VLSI power supply networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:126-132 [Journal]
  64. Ken Tseng, Mark Horowitz
    False coupling exploration in timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1795-1805 [Journal]
  65. Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
    Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1998, v:16, n:2, pp:170-205 [Journal]
  66. Marc Levoy, Billy Chen, Vaibhav Vaish, Mark Horowitz, Ian McDowall, Mark T. Bolas
    Synthetic aperture confocal imaging. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Graph., 2004, v:23, n:3, pp:825-834 [Journal]
  67. Marc Levoy, Ren Ng, Andrew Adams, Matthew Footer, Mark Horowitz
    Light field microscopy. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Graph., 2006, v:25, n:3, pp:924-934 [Journal]
  68. Pradeep Sen, Billy Chen, Gaurav Garg, Stephen R. Marschner, Mark Horowitz, Marc Levoy, Hendrik P. A. Lensch
    Dual photography. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Graph., 2005, v:24, n:3, pp:745-755 [Journal]
  69. Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Eino-Ville Talvala, Emilio Antunez, Adam Barth, Andrew Adams, Mark Horowitz, Marc Levoy
    High performance imaging using large camera arrays. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Graph., 2005, v:24, n:3, pp:765-776 [Journal]
  70. Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman
    Robust Energy-Efficient Adder Topologies. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:16-28 [Conf]
  71. Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz
    Chip Multi-Processor Generator. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:262-263 [Conf]
  72. Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis
    Comparing memory systems for chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:358-368 [Conf]
  73. Eino-Ville Talvala, Andrew Adams, Mark Horowitz, Marc Levoy
    Veiling glare in high dynamic range imaging. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Graph., 2007, v:26, n:3, pp:37- [Journal]

  74. The case for simple, visible cache coherency. [Citation Graph (, )][DBLP]


  75. Fortifying analog models with equivalence checking and coverage analysis. [Citation Graph (, )][DBLP]


  76. Intent-leveraged optimization of analog circuits via homotopy. [Citation Graph (, )][DBLP]


  77. Why design must change: Rethinking digital design. [Citation Graph (, )][DBLP]


  78. An integrated framework for joint design space exploration of microarchitecture and circuits. [Citation Graph (, )][DBLP]


  79. In field, energy-performance tunable FPGA architectures. [Citation Graph (, )][DBLP]


  80. A memory system design framework: creating smart memories. [Citation Graph (, )][DBLP]


  81. Understanding sources of inefficiency in general-purpose chips. [Citation Graph (, )][DBLP]


  82. Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. [Citation Graph (, )][DBLP]


  83. Processor Performance Modeling using Symbolic Simulation. [Citation Graph (, )][DBLP]


  84. Verification of chip multiprocessor memory systems using a relaxed scoreboard. [Citation Graph (, )][DBLP]


  85. Using a configurable processor generator for computer architecture prototyping. [Citation Graph (, )][DBLP]


  86. Why design must change: rethinking digital design. [Citation Graph (, )][DBLP]


  87. Towards an explanatory and computational theory of scientific discovery [Citation Graph (, )][DBLP]


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