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Journals in DBLP

Microelectronics Reliability
2005, volume: 45, number: 7-8

  1. Douglas Brisbin, Andy Strachan, Prasad Chaparala
    Optimizing the hot carrier reliability of N-LDMOS transistor arrays. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1021-1032 [Journal]
  2. D. Q. Kelly, S. Dey, D. Onsongo, S. K. Banerjee
    Considerations for evaluating hot-electron reliability of strained Si n-channel MOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1033-1040 [Journal]
  3. Wataru Mizubayashi, Naoki Yasuda, Kenji Okada, Hiroyuki Ota, Hirokazu Hisamatsu, Kunihiko Iwamoto, Koji Tominaga, Katsuhiko Yamamoto, Tsuyoshi Horikawa, Toshihide Nabatame
    Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1041-1050 [Journal]
  4. Se Jong Rhee, Jack C. Lee
    Threshold voltage instability characteristics of HfO2 dielectrics n-MOSFETs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1051-1060 [Journal]
  5. M. H. Lin, Y. L. Lin, K. P. Chang, K. C. Su, Tahui Wang
    Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1061-1078 [Journal]
  6. Guotao Wang, Paul S. Ho, Steven Groothuis
    Chip-packaging interaction: a critical concern for Cu/low k packaging. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1079-1093 [Journal]
  7. Andrea Chimenton, Piero Olivo
    Reliability of erasing operation in NOR-Flash memories. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1094-1108 [Journal]
  8. H. Aono, E. Murakami, K. Okuyama, A. Nishida, M. Minami, Y. Ooji, K. Kubota
    Modeling of NBTI saturation effect and its impact on electric field dependence of the lifetime. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1109-1114 [Journal]
  9. Shyue Seng Tan, Tu Pei Chen, Lap Chan
    Dynamic NBTI lifetime model for inverter-like waveform. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1115-1118 [Journal]
  10. Yao-Jen Lee, Tien-Sheng Chao, Tiao-Yuan Huang
    High voltage applications and NBTI effects of DT-pMOSFETS with reverse Schottky substrate contacts. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1119-1123 [Journal]
  11. Albena Paskaleva, Anton J. Bauer, Martin Lemberger
    Conduction mechanisms and an evidence for phonon-assisted conduction process in thin high-k HfxTiySizO films. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1124-1133 [Journal]
  12. H. Y. Li, Y. J. Su, C. F. Tsang, S. M. Sohan, V. N. Bliznetsov, L. Zhang
    Process improvement of 0.13mum Cu/Low K (Black DiamondTM) dual damascene interconnection. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1134-1143 [Journal]
  13. C. S. Ho, Kuo-Yin Huang, Ming Tang, Juin J. Liou
    An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1144-1149 [Journal]
  14. Y. J. Song, H. J. Joo, S. K. Kang, H. H. Kim, J. H. Park, Y. M. Kang, E. Y. Kang, S. Y. Lee, K. Kim
    Electrical properties of highly reliable 32Mb FRAM with advanced capacitor technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1150-1153 [Journal]
  15. A. R. Saha, S. Chattopadhyay, G. K. Dalapati, S. K. Nandi, C. K. Maiti
    An investigation of electrical and structural properties of Ni-germanosilicided Schottky diode. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1154-1160 [Journal]
  16. M. Estrada, A. Cerdeira, L. Resendiz, Benjamín Iñiguez, L. F. Marzal, J. Pallares
    Effect of localized traps on the anomalous behavior of the transconductance in nanocrystalline TFTs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1161-1166 [Journal]
  17. Nicolas Valdaperez, Jean-Marc Routoure, Daniel Bloyet, Régis Carin, Serge Bardy
    Size effects on the DC characteristics and low frequency noise of double polysilicon NPN bipolar transistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1167-1173 [Journal]
  18. Peter Jacob, Uwe Thiemann, Joachim C. Reiner
    Electrostatic discharge directly to the chip surface, caused by automatic post-wafer processing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1174-1180 [Journal]
  19. J. Urresti, S. Hidalgo, D. Flores, J. Roig, I. Cortés, J. Rebollo
    Lateral punch-through TVS devices for on-chip protection in low-voltage applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1181-1186 [Journal]
  20. Martin Sauter
    Determination of self-heating and thermal resistance in polycrystalline and bulk silicon resistors by DC measurements. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1187-1193 [Journal]
  21. Walter Smetana, Roland Reicher, H. Homolka
    Improving reliability of thick film initiators for automotive applications based on FE-analyses. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1194-1201 [Journal]
  22. H. Niemiec, A. Bulgheroni, M. Caccia, P. Grabiec, M. Grodner, M. Jastrzab, W. Kucewicz, K. Kucharski, S. Kuta, J. Marczewski
    Monolithic active pixel sensor realized in SOI technology - concept and verification. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1202-1207 [Journal]
  23. Masayuki Kitajima, Tadaaki Shono
    Reliability study of new SnZnAl lead-free solders used in CSP packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1208-1214 [Journal]
  24. Xiaowu Zhang, E. H. Wong, Ranjan Rajoo, Mahadevan K. Iyer, J. F. J. M. Caers, X. J. Zhao
    Development of process modeling methodology for flip chip on flex interconnections with non-conductive adhesives. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1215-1221 [Journal]
  25. Y. F. Yao, B. Njoman, K. H. Chua, T. Y. Lin
    New encapsulation development for fine pitch IC devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1222-1229 [Journal]
  26. Wenming Zhang, Guang Meng, Hongguang Li
    Electrostatic micromotor and its reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1230-1242 [Journal]
  27. Sheng-Jen Hsieh, Sung-Ling Huang
    A methodology for microcontroller signal frequency stress prediction. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1243-1251 [Journal]
  28. M. Serényi, J. Betko, Á. Nemcsics, N. Q. Khanh, D. K. Basa, M. Morvic
    Study on the RF Sputtered hydrogenated amorphous silicon-germanium thin films. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1252-1256 [Journal]
  29. G. Janczyk
    Bipolar mechanisms present in short channel SOI-MOSFET transistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1257-1263 [Journal]
  30. Mansour Jaragh, Ahmed Hasswa
    Implementation, analysis and performance evaluation of the IRP replacement policy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1264-1269 [Journal]
  31. Mile K. Stojcev
    Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPs), Tilman Glokler, Heinrich Meyr, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7730-0, Hardcover, pp 234, plus XX. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1270-1271 [Journal]
  32. Mile K. Stojcev
    Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1272- [Journal]
  33. Mile K. Stojcev
    Alberto Leon-Garcia, Indra Widjaja, Communication Networks: Fundamental Concepts and Key Architectures, Second edition, McGraw Hill Higher Education, Boston, 2004, ISBN 0-07-119848-2. Hardcover, pp 900, plus XXVII. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:7-8, pp:1273-1274 [Journal]
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