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Zoran A. Salcic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Flavius Gruian, Zoran A. Salcic
    Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:281-294 [Conf]
  2. Lei Yang, Morteza Biglari-Abhari, Zoran A. Salcic
    A Power-Efficient Processor Core for Reactive Embedded Applications. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:131-142 [Conf]
  3. Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari
    REMIC: design of a reactive embedded microprocessor core. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:977-981 [Conf]
  4. Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic
    HiDRA: A New Architecture for Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:164-170 [Conf]
  5. Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne
    Towards direct execution of esterel programs on reactive processors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:240-248 [Conf]
  6. Zoran A. Salcic, Partha S. Roop
    Customizing Processor Cores to Support Reactivity. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:194-202 [Conf]
  7. R. Bruce Maunder, Zoran A. Salcic, George G. Coghill
    FPLD HDL synthesis employing high-level evolutionary algorithm optimisation. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:265-273 [Conf]
  8. R. Bruce Maunder, Zoran A. Salcic, George G. Coghill
    High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:377-384 [Conf]
  9. Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli
    REFLIX: A Processor Core for Reactive Embedded Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:945-945 [Conf]
  10. Zoran A. Salcic, R. Bruce Maunder
    CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:280-289 [Conf]
  11. Roshan Duraisamy, Zoran A. Salcic, Miguel Morales-Sandoval, Claudia Feregrino Uribe
    A Fast Elliptic Curve Based Key Agreement Protocol-on-Chip (PoC) for Securing Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:154-161 [Conf]
  12. Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid
    A Scheduler Support Unit for Reactive Microprocessors. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:368-372 [Conf]
  13. Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic
    Distributed Embedded Intelligence Room with Multi-agent Cooperative Learning. [Citation Graph (0, 0)][DBLP]
    UIC, 2006, pp:147-156 [Conf]
  14. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:461-464 [Conf]
  15. Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli
    A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:189-194 [Conf]
  16. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    Modeling Embedded Systems: From SystemC and Esterel to DFCharts. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:348-358 [Journal]
  17. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    A New Model for Heterogeneous Embedded Systems - What Esterel and SyncCharts Need to Become a Suitable Specification Platform. [Citation Graph (0, 0)][DBLP]
    International Journal of Software Engineering and Knowledge Engineering, 2005, v:15, n:2, pp:405-410 [Journal]
  18. Zoran A. Salcic, Jayanthi Sivaswamy
    IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1999, v:5, n:6, pp:385-395 [Journal]
  19. Jayanthi Sivaswamy, Zoran A. Salcic, K. L. Ling
    A Real-Time Implementation of Nonlinear Unsharp Masking with FPLDs. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2001, v:7, n:2, pp:195-202 [Journal]
  20. Zoran A. Salcic
    High-speed customizable fuzzy-logic processor: architecture and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part A, 2001, v:31, n:6, pp:731-737 [Journal]
  21. Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari
    HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:2, pp:72-85 [Journal]
  22. Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli
    REFLIX: a processor core with native support for control-dominated embedded applications. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:1, pp:13-25 [Journal]
  23. Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic
    Multi-agent System with Hybrid Intelligence Using Neural Network and Fuzzy Inference Techniques. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2007, pp:473-482 [Conf]
  24. Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic
    The SystemJ approach to system-level design. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:149-158 [Conf]
  25. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    McCharts and Multiclock FSMs for modeling large scale systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:3-12 [Conf]
  26. Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic
    Multi-agent Software Control System with Hybrid Intelligence for Ubiquitous Intelligent Environments. [Citation Graph (0, 0)][DBLP]
    UIC, 2007, pp:1046-1055 [Conf]

  27. Rapid Energy Estimation for Embedded Soft-core Microprocessors. [Citation Graph (, )][DBLP]


  28. A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution. [Citation Graph (, )][DBLP]


  29. Modelling Heterogeneous Embedded Systems in DFCarts. [Citation Graph (, )][DBLP]


  30. Energy Efficiency of Collaborative Communication with Imperfect Frequency Synchronization in Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  31. STARPro - A new multithreaded direct execution platform for Esterel. [Citation Graph (, )][DBLP]


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