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Hossein Pedram: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Amir Hossein Hadad, Mehdi Dehghan, Hossein Pedram
    Locating Performance Monitoring Mobile Agents in Scalable Active Networks. [Citation Graph (0, 0)][DBLP]
    AAIM, 2005, pp:472-482 [Conf]
  2. Amir Rezaeinia, Vali Fatemi, Hossein Pedram, Babak Sadeghian, Mohsen Naderi
    Asynchronous vs. Synchronous Design of RSA. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:100-105 [Conf]
  3. Arash Saifhashemi, Hossein Pedram
    Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:330-333 [Conf]
  4. Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:269- [Conf]
  5. Shervin Sheidaei, Hamid Noori, Ahmad Akbari, Hossein Pedram
    Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:388-397 [Conf]
  6. Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:296-301 [Conf]
  7. Atabak Mahram, Mehrdad Najibi, Hossein Pedram
    An asynchronous fpga logic cell implementation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:176-179 [Conf]
  8. Mehrdad Najibi, Kamran Saleh, Hossein Pedram
    Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:299-304 [Conf]
  9. Mehrdad Najibi, M. Salehi, Ali Afzali-Kusha, Massoud Pedram, Seid Mehdi Fakhraie, Hossein Pedram
    Dynamic voltage and frequency management based on variable update intervals for frequency setting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:755-760 [Conf]
  10. Esmail Amini, Mehrdad Najibi, Hossein Pedram
    Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:193-199 [Conf]
  11. Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram
    A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:471-472 [Conf]
  12. Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram
    Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:422-427 [Conf]
  13. Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari
    An Asynchronous Viterbi Decoder for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:471-480 [Conf]
  14. Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:63-69 [Conf]
  15. Behnam Ghavami, Hossein Pedram
    An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:330-339 [Conf]
  16. Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram
    A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:463-473 [Conf]

  17. A Fault Injection Attitude based on Background Debug Mode in Embedded Systems. [Citation Graph (, )][DBLP]


  18. A DDoS-Aware IDS Model Based on Danger Theory and Mobile Agents. [Citation Graph (, )][DBLP]


  19. Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing. [Citation Graph (, )][DBLP]


  20. Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. [Citation Graph (, )][DBLP]


  21. Fault injection-based evaluation of a synchronous NoC router. [Citation Graph (, )][DBLP]


  22. Design of dual threshold voltages asynchronous circuits. [Citation Graph (, )][DBLP]


  23. Statistical static performance analysis of asynchronous circuits considering process variation. [Citation Graph (, )][DBLP]


  24. Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading. [Citation Graph (, )][DBLP]


  25. Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation. [Citation Graph (, )][DBLP]


  26. Investigation of Transient Fault Effects in an Asynchronous NoC Router. [Citation Graph (, )][DBLP]


  27. An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. [Citation Graph (, )][DBLP]


  28. A New Method for Creating Efficient Security Policies in Virtual Private Network. [Citation Graph (, )][DBLP]


  29. Mobile object tracking techniques in wireless sensor networks. [Citation Graph (, )][DBLP]


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