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Ramesh C. Tekumalla:
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Publications of Author
- Ramesh C. Tekumalla, Premachandran R. Menon
Test generation for primitive path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:636-641 [Conf]
- Ramesh C. Tekumalla, Premachandran R. Menon
On primitive fault test generation in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:275-282 [Conf]
- Ramesh C. Tekumalla, Premachandran R. Menon
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. [Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:648-653 [Conf]
- Ramesh C. Tekumalla
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures. [Citation Graph (0, 0)][DBLP] ITC, 2003, pp:737-744 [Conf]
- Ramesh C. Tekumalla, Scott Davidson
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. [Citation Graph (0, 0)][DBLP] ITC, 2002, pp:993-1002 [Conf]
- Ramesh C. Tekumalla, Premachandran R. Menon
Delay Testing with Clock Control: An Alternative to Enhanced Scan. [Citation Graph (0, 0)][DBLP] ITC, 1997, pp:454-462 [Conf]
- Ramesh C. Tekumalla, Premachandran R. Menon
Robust testability of primitive faults using test points. [Citation Graph (0, 0)][DBLP] ITC, 1999, pp:260-268 [Conf]
- Ramesh C. Tekumalla
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules. [Citation Graph (0, 0)][DBLP] VLSI Design, 2006, pp:824-827 [Conf]
- Ramesh C. Tekumalla, Premachandran R. Menon
Identifying Redundant Path Delay Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 1996, pp:406-411 [Conf]
- Ramesh C. Tekumalla
On Test Set Generation for Efficient Path Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP] VTS, 2000, pp:343-348 [Conf]
- Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar
On Diagnosing Path Delay Faults in an At-Speed Environment. [Citation Graph (0, 0)][DBLP] VTS, 2001, pp:28-33 [Conf]
- Ramesh C. Tekumalla, Premachandran R. Menon
On Redundant Path Delay Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2000, v:49, n:3, pp:277-282 [Journal]
- Ramesh C. Tekumalla, Premachandran R. Menon
Identification of primitive faults in combinational and sequentialcircuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1426-1442 [Journal]
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