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Publications of Author

1. Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
   Modeling of Interconnection Networks in Massively Parallel Processor Architectures. [Citation Graph (0, 0)][DBLP]
   ARCS, 2007, pp:268-282 [Conf]
   
2. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
   A Compilation Framework for a Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:1058-1067 [Conf]
   
3. Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
   Concurrent Design of Hardware/Software Dedicated Systems. [Citation Graph (0, 0)][DBLP]
   FPL, 1996, pp:410-414 [Conf]
   
4. S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres
   Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. [Citation Graph (0, 0)][DBLP]
   VLSI, 1999, pp:407-414 [Conf]
   
5. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
   A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2001, pp:51-62 [Conf]
   
6. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
   DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2002, pp:- [Conf]
   
7. Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys
   A low-power and high-speed quaternary interconnection link using efficient converters. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:4689-4692 [Conf]
   
8. Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys
   Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:334-339 [Conf]
   
9. Sébastien Pillement, Daniel Chillet, Olivier Sentieys
   Behavioral IP Specification and Integration Framework for High-Level Design Reuse. [Citation Graph (0, 0)][DBLP]
   ISQED, 2002, pp:388-393 [Conf]
   
10. Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny
    Clear Stream towards Dynamically Reconfigurable Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:98-104 [Conf]
    
11. François Verdier, Jean-Christophe Prévotet, Amine Benkhelifa, Daniel Chillet, Sébastien Pillement
    Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:71-78 [Conf]
    
12. Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
    Fast Prototyping: A Case Study - The JPEG Compression Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:87-0 [Conf]
    
13. Raphaël David, Dominique Lavenier, Sébastien Pillement
    Du microprocesseur au circuit FPGA. Une analyse sous l'angle de la reconfiguration. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2005, v:24, n:4, pp:395-422 [Journal]
    
14. Jean-Marc Philippe, E. Kinvi-Boh, Sébastien Pillement, Olivier Sentieys
    An energy-efficient ternary interconnection link for asynchronous systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
15. 
    xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]
    
    
16. 
    High-Level Exploration for Dynamic Reconfiguration Management. [Citation Graph (, )][DBLP]
    
    
17. 
    A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. [Citation Graph (, )][DBLP]
    
    
18. 
    Design of a fault-tolerant coarse-grained. [Citation Graph (, )][DBLP]
    
    
19. 
    Efficient dynamic reconfiguration for multi-context embedded FPGA. [Citation Graph (, )][DBLP]
    
    
20. 
    A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip. [Citation Graph (, )][DBLP]
    
    
21. 
    A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. [Citation Graph (, )][DBLP]