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Lionel Torres: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
    A parallelized way to provide data encryption and integrity checking on a processor-memory bus. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:506-509 [Conf]
  2. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud
    Hardware Engines for Bus Encryption: A Survey of Existing Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:40-45 [Conf]
  3. Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy
    Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:553-558 [Conf]
  4. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet
    PE-ICE: Parallelized Encryption and Integrity Checking Engine. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:143-144 [Conf]
  5. Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli
    Architecture for Highly Reliable Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:75-80 [Conf]
  6. Alex Ngouanga, Gilles Sassatelli, Lionel Torres, André Soares, Altamiro Amadeu Susin
    A Contextual Resources use: a Proof of Concept through the APACHES' Platform. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:44-49 [Conf]
  7. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon
    Dynamic hardware multiplexing for coarse grain reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:270- [Conf]
  8. Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    Magnetic tunnelling junction based FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:123-130 [Conf]
  9. Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli
    Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:687-690 [Conf]
  10. Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:703-706 [Conf]
  11. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny
    A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:722-732 [Conf]
  12. Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
    Concurrent Design of Hardware/Software Dedicated Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:410-414 [Conf]
  13. Gilles Sassatelli, Lionel Torres, Jérôme Galy, Gaston Cambon, Camille Diou
    The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:409-419 [Conf]
  14. Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne
    Influence of Locig Block Layout Architecture on FPGA Performance. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:34-44 [Conf]
  15. Camille Diou, Lionel Torres, Michel Robert
    A Wavelet Core for Video Processing. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  16. S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres
    Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:407-414 [Conf]
  17. Camille Diou, Lionel Torres, Michel Robert
    Implementation of a Wavelet Transform Architecture for Image Processing. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:101-112 [Conf]
  18. Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy
    Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:63-74 [Conf]
  19. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon
    Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:176- [Conf]
  20. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon
    Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  21. Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frédéric Bancel
    Securing embedded programmable gate arrays in secure circuits. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  22. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker
    Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:251-256 [Conf]
  23. Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    New non-volatile FPGA concept using Magnetic Tunneling Junction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:269-276 [Conf]
  24. Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert
    HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:21-28 [Conf]
  25. Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    Technological hybridization for efficient runtime reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:29-34 [Conf]
  26. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
    A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:267-279 [Conf]
  27. Christel-loic Tisse, Lionel Martin, Lionel Torres, Michel Robert
    Iris recognition system for person identification. [Citation Graph (0, 0)][DBLP]
    PRIS, 2002, pp:186-199 [Conf]
  28. Benoît Badrignans, Daniel Mesquita, Jean-Claude Bajard, Lionel Torres, Gilles Sassatelli, Michel Robert
    A Parallel and Secure Architecture for Asymmetric Cryptography. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:220-224 [Conf]
  29. Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli
    Non-volatile SRAM-FPGA based on magnetic tunnelling junction. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:113-120 [Conf]
  30. Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    Remanent SRAM Structure for Runtime Reconfigurable FPGA. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:124-130 [Conf]
  31. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
    Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:69-75 [Conf]
  32. Viktor Fischer, Lionel Torres, Daniel Mesquita
    Flexible security and its technology limits. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:243-248 [Conf]
  33. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes
    A new hardware countermeasure for masking power signatures of crypto cores. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:169-176 [Conf]
  34. Nicolas Valette, Lionel Torres, Frédéric Bancel, Nicolas Bérard
    Integration of Reconfigurable Logic on Secure Circuits. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:163-168 [Conf]
  35. Nicolas Valette, Lionel Torres, Gilles Sassatelli, S. Bancel
    How to Secure Embedded Programmable Gate Arrays? [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:52-59 [Conf]
  36. Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
    Fast Prototyping: A Case Study - The JPEG Compression Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:87-0 [Conf]
  37. Gilles Sassatelli, Gaston Cambon, Jérôme Galy, Lionel Torres
    A Dynamically Reconfigurable Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:32-37 [Conf]
  38. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon
    Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:128-137 [Conf]
  39. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes
    Current mask generation: a transistor level security against DPA attacks. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:115-120 [Conf]
  40. Daniel Mesquita, Lionel Torres, Fernando Gehm Moraes, Gilles Sassatelli, Michel Robert
    Are coarse grain reconfigurable architectures suitable for cryptography? [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:276-281 [Conf]
  41. Solaiman Rahim, Bruno Rouzeyre, Lionel Torres
    A Flip-Flop Matching Engine to Verify Sequential Optimizations. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  42. Lionel Torres, El-Bay Bourennane, Michel Robert, Michel Paindavoine
    A Recursive Digital Filter Implementation for Noisy and Blurred Images. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1998, v:4, n:3, pp:181-191 [Journal]
  43. Reouven Elbaz, David Champagne, Ruby B. Lee, Lionel Torres, Gilles Sassatelli, Pierre Guillemin
    TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2007, pp:289-302 [Conf]
  44. Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli
    Evaluation of design for reliability techniques in embedded flash memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1593-1598 [Conf]
  45. Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes
    A Leak Resistant Architecture Against Side Channel Attacks. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  46. Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Moraes
    A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  47. Eduardo Wanderley Neto, Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet
    IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:138-145 [Conf]
  48. Nicolas Saint-Jean, Camille Jalier, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert
    HS Scale: A run-time adaptable MP-SoC architecture. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:39-46 [Conf]
  49. Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert
    Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:88-95 [Conf]
  50. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes
    Current Mask Generation: an Analog Circuit to Thwart DPA Attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:317-330 [Conf]
  51. Alex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin
    Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:134-145 [Conf]
  52. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud
    Hardware Engines for Bus Encryption: A Survey of Existing Techniques [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  53. When Failure Analysis Meets Side-Channel Attacks. [Citation Graph (, )][DBLP]


  54. Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. [Citation Graph (, )][DBLP]


  55. Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC. [Citation Graph (, )][DBLP]


  56. Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. [Citation Graph (, )][DBLP]


  57. Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. [Citation Graph (, )][DBLP]


  58. Differential Power Analysis enhancement with statistical preprocessing. [Citation Graph (, )][DBLP]


  59. Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs. [Citation Graph (, )][DBLP]


  60. Convergence analysis of run-time distributed optimization on adaptive systems using game theory. [Citation Graph (, )][DBLP]


  61. A non-volatile run-time FPGA using thermally assisted switching MRAMS. [Citation Graph (, )][DBLP]


  62. Secure FPGA configuration architecture preventing system downgrade. [Citation Graph (, )][DBLP]


  63. Bio-inspiration helps computers: A new machine. [Citation Graph (, )][DBLP]


  64. MPI-Based Adaptive Task Migration Support on the HS-Scale System. [Citation Graph (, )][DBLP]


  65. Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory. [Citation Graph (, )][DBLP]


  66. Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. [Citation Graph (, )][DBLP]


  67. Evaluating the robustness of secure triple track logic through prototyping. [Citation Graph (, )][DBLP]


  68. Secure update Mechanism for Remote Update of FPGA-Based System. [Citation Graph (, )][DBLP]


  69. Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC. [Citation Graph (, )][DBLP]


  70. MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs. [Citation Graph (, )][DBLP]


  71. Forward-Secure Content Distribution to Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  72. Triple Rail Logic Robustness against DPA. [Citation Graph (, )][DBLP]


  73. Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs. [Citation Graph (, )][DBLP]


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