The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Timothy Sherwood: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ted Huffmire, Timothy Sherwood
    Wavelet-based phase classification. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:95-104 [Conf]
  2. Timothy Sherwood, Erez Perelman, Brad Calder
    Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:3-14 [Conf]
  3. Timothy Sherwood, Erez Perelman, Greg Hamerly, Brad Calder
    Automatically characterizing large scale program behavior. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:45-57 [Conf]
  4. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
    Introspective 3D chips. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:264-273 [Conf]
  5. Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder
    Reducing code size with echo instructions. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:84-94 [Conf]
  6. Timothy Sherwood, Brad Calder
    Patchable instruction ROM architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:24-33 [Conf]
  7. Timothy Sherwood, Mark Oskin, Brad Calder
    Balancing design options with Sherpa. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:57-68 [Conf]
  8. Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Timothy Sherwood, Suleyman Sair
    Improving the performance and power efficiency of shared helpers in CMPs. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:345-356 [Conf]
  9. Greg Hoover, Forrest Brewer, Timothy Sherwood
    Extensible control architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:323-333 [Conf]
  10. Greg Hoover, Forrest Brewer, Timothy Sherwood
    A case study of multi-threading in the embedded space. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:357-367 [Conf]
  11. Shashidhar Mysore, Banit Agrawal, Timothy Sherwood, Nisheeth Shrivastava, Subhash Suri
    Profiling over Adaptive Ranges. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:147-158 [Conf]
  12. Priya Nagpurkar, Chandra Krintz, Timothy Sherwood
    Phase-Aware Remote Profiling. [Citation Graph (0, 0)][DBLP]
    CGO, 2005, pp:191-202 [Conf]
  13. Mathew Mason, Timothy Sherwood, Mohammad Rahman, Miroslava Vomela
    Development of an Olympic audience judging system. [Citation Graph (0, 0)][DBLP]
    CHI Extended Abstracts, 2004, pp:1626-1630 [Conf]
  14. Timothy Sherwood, Farilee Mintz, Miroslava Vomela
    Project VIRGO: creation of a surrogate companion for the elderly. [Citation Graph (0, 0)][DBLP]
    CHI Extended Abstracts, 2005, pp:2104-2108 [Conf]
  15. Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
    A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:991-996 [Conf]
  16. Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner
    MP core: algorithm and design techniques for efficient channel estimation in wireless applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:297-302 [Conf]
  17. Yan Meng, Timothy Sherwood, Ryan Kastner
    Leakage power reduction of embedded memories on FPGAs through location assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:612-617 [Conf]
  18. Wenrui Gong, Yan Meng, Gang Wang, Ryan Kastner, Timothy Sherwood
    Data Partitioning and Optimizations for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:239-242 [Conf]
  19. Ted Huffmire, Shreyas Prasad, Timothy Sherwood, Ryan Kastner
    Policy-Driven Memory Protection for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ESORICS, 2006, pp:461-478 [Conf]
  20. Timothy Sherwood, Brad Calder
    ToolBlocks: An Infrastructure for the Construction of Memory Hierarchy Analysis Tools (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:70-74 [Conf]
  21. Satish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, George Varghese
    Catching Accurate Profiles in Hardwar. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:269-280 [Conf]
  22. Suleyman Sair, Timothy Sherwood, Brad Calder
    Quantifying Load Stream Behavior. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:197-0 [Conf]
  23. Yan Meng, Timothy Sherwood, Ryan Kastner
    On the Limits of Leakage Power Reduction in Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:154-165 [Conf]
  24. Mark Oskin, Frederic T. Chong, Timothy Sherwood
    ActiveOS: Virtualizing Intelligent Memory. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:202-0 [Conf]
  25. Anahita Shayesteh, Eren Kursun, Timothy Sherwood, Suleyman Sair, Glenn Reinman
    Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:17-23 [Conf]
  26. Timothy Sherwood, Brad Calder, Joel S. Emer
    Reducing cache misses using hardware and software page placement. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:155-164 [Conf]
  27. Nathan Tuck, Timothy Sherwood, Brad Calder, George Varghese
    Deterministic Memory-Efficient String Matching Algorithms for Intrusion Detection. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2004, pp:- [Conf]
  28. Mark Oskin, Frederic T. Chong, Timothy Sherwood
    Active Pages: A Computation Model for Intelligent Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:192-203 [Conf]
  29. Timothy Sherwood, Brad Calder
    Automated design of finite state machine predictors for customized processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:86-97 [Conf]
  30. Timothy Sherwood, Suleyman Sair, Brad Calder
    Phase Tracking and Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:336-347 [Conf]
  31. Timothy Sherwood, George Varghese, Brad Calder
    A Pipelined Memory Architecture for High Throughput Network Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:288-299 [Conf]
  32. Lin Tan, Timothy Sherwood
    A High Throughput String Matching Architecture for Intrusion Detection and Prevention. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:112-122 [Conf]
  33. Timothy Sherwood, Brad Calder
    Loop Termination Prediction. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:73-87 [Conf]
  34. Michael Van Biesbrouck, Timothy Sherwood, Brad Calder
    A co-phase matrix to guide simultaneous multithreading simulation. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:45-56 [Conf]
  35. Timothy Sherwood, Suleyman Sair, Brad Calder
    Predictor-directed stream buffers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:42-53 [Conf]
  36. Banit Agrawal, Timothy Sherwood
    Virtually Pipelined Network Memory. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:197-207 [Conf]
  37. Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, Timothy Sherwood
    Low-Overhead Core Swapping for Thermal Management. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:46-60 [Conf]
  38. Erez Perelman, Greg Hamerly, Michael Van Biesbrouck, Timothy Sherwood, Brad Calder
    Using SimPoint for accurate and efficient simulation. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2003, pp:318-319 [Conf]
  39. Ted Huffmire, Brett Brotherton, Gang Wang, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine
    Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Security and Privacy, 2007, pp:281-295 [Conf]
  40. Greg Hamerly, Erez Perelman, Jeremy Lau, Brad Calder, Timothy Sherwood
    Using Machine Learning to Guide Architecture Simulation. [Citation Graph (0, 0)][DBLP]
    Journal of Machine Learning Research, 2006, v:7, n:, pp:343-378 [Journal]
  41. Timothy Sherwood, Erez Perelman, Greg Hamerly, Suleyman Sair, Brad Calder
    Discovering and Exploiting Program Phases. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:84-93 [Journal]
  42. Timothy Sherwood, Joshua J. Yi
    Guest Editors' Introduction: Computer Architecture Simulation and Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:4, pp:5-7 [Journal]
  43. Lin Tan, Timothy Sherwood
    Architectures for Bit-Split String Scanning in Intrusion Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:110-117 [Journal]
  44. Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood
    Dynamically configurable shared CMP helper engines for improved performance. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:70-79 [Journal]
  45. Yan Meng, Timothy Sherwood, Ryan Kastner
    Exploring the limits of leakage power reduction in caches. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:3, pp:221-246 [Journal]
  46. Priya Nagpurkar, Hussam Mousa, Chandra Krintz, Timothy Sherwood
    Efficient remote profiling for resource-constrained devices. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:1, pp:35-66 [Journal]
  47. Lin Tan, Brett Brotherton, Timothy Sherwood
    Bit-split string-matching engines for intrusion detection and prevention. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:1, pp:3-34 [Journal]
  48. Suleyman Sair, Timothy Sherwood, Brad Calder
    A Decoupled Predictor-Directed Stream Prefetching Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:260-276 [Journal]
  49. Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
    Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1355-1371 [Journal]
  50. Greg Hoover, Forrest Brewer, Timothy Sherwood
    Towards understanding architectural tradeoffs in MEMS closed-loop feedback control. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:95-102 [Conf]
  51. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
    3D Integration for Introspection. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:77-83 [Journal]
  52. Yan Meng, Wenrui Gong, Ryan Kastner, Timothy Sherwood
    Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:238-248 [Journal]

  53. Quantifying the Potential of Program Analysis Peripherals. [Citation Graph (, )][DBLP]


  54. Understanding and visualizing full systems with data flow tomography. [Citation Graph (, )][DBLP]


  55. Complete information flow tracking from the gates up. [Citation Graph (, )][DBLP]


  56. Theoretical analysis of gate level information flow tracking. [Citation Graph (, )][DBLP]


  57. VrtProf: Vertical Profiling for System Virtualization. [Citation Graph (, )][DBLP]


  58. Guiding Architectural SRAM Models. [Citation Graph (, )][DBLP]


  59. Multi-execution: multicore caching for data-similar executions. [Citation Graph (, )][DBLP]


  60. Conflict-Avoidance in Multicore Caching for Data-Similar Executions. [Citation Graph (, )][DBLP]


  61. Modeling TCAM power for next generation network devices. [Citation Graph (, )][DBLP]


  62. Motivation for Variable Length Intervals and Hierarchical Phase Behavior. [Citation Graph (, )][DBLP]


  63. Execution leases: a hardware-supported mechanism for enforcing strong non-interference. [Citation Graph (, )][DBLP]


  64. A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags. [Citation Graph (, )][DBLP]


  65. Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation. [Citation Graph (, )][DBLP]


  66. Exploring the Processor and ISA Design for Wireless Sensor Network Applications. [Citation Graph (, )][DBLP]


  67. Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems. [Citation Graph (, )][DBLP]


  68. Automata-Theoretic Analysis of Bit-Split Languages for Packet Scanning. [Citation Graph (, )][DBLP]


  69. Whiteboards that compute: A workload analysis. [Citation Graph (, )][DBLP]


  70. Trustworthy System Security through 3-D Integrated Hardware. [Citation Graph (, )][DBLP]


  71. Enforcing memory policy specifications in reconfigurable hardware. [Citation Graph (, )][DBLP]


  72. Managing Security in FPGA-Based Embedded Systems. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.011secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002