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Michael S. Schlansker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker
    A Distributed Control Path Architecture for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:197-206 [Conf]
  2. Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:238-247 [Conf]
  3. Shail Aditya, Michael S. Schlansker
    ShiftQ: a bufferred interconnect for custom loop accelerators. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:158-167 [Conf]
  4. B. Ramakrishna Rau, Michael S. Schlansker
    Embedded Computing: New Directions in Architecture and Automation. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:225-244 [Conf]
  5. B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen
    The Cydram 5 Stride-Insensitive Memory System. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:242-246 [Conf]
  6. Michael S. Schlansker, Vinod Kathail
    Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. [Citation Graph (0, 0)][DBLP]
    LCPC, 1993, pp:406-429 [Conf]
  7. Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker
    Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:58-67 [Conf]
  8. David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker
    Global Predicate Analysis and Its Application to Register Allocation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:114-125 [Conf]
  9. Richard Johnson, Michael S. Schlansker
    Analysis Techniques for Predicated Code. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:100-113 [Conf]
  10. B. Natarajan, Michael S. Schlansker
    Spill-free parallel scheduling of basic blocks. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:119-124 [Conf]
  11. B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
    Code generation schema for modulo scheduled loops. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:158-169 [Conf]
  12. Michael S. Schlansker
    In Memory of Bob Rau. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:165-168 [Conf]
  13. Michael S. Schlansker, Vinod Kathail
    Critical path reduction for scalar programs. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:57-69 [Conf]
  14. Michael S. Schlansker, Vinod Kathail, Sadun Anik
    Height reduction of control recurrences for ILP processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:40-51 [Conf]
  15. Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Mike Schlansker, Brad Calder
    Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:235-246 [Conf]
  16. B. Ramakrishna Rau, M. Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker
    Register Allocation for Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    PLDI, 1992, pp:283-299 [Conf]
  17. Michael S. Schlansker, Scott A. Mahlke, Richard Johnson
    Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. [Citation Graph (0, 0)][DBLP]
    PLDI, 1999, pp:155-168 [Conf]
  18. Parthasarathy P. Tirumalai, M. Lee, Michael S. Schlansker
    Parallelization of loops with exits on pipelined architectures. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:200-212 [Conf]
  19. Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe
    Challenges to Combining General-Purpose and Multimedia Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:33-37 [Journal]
  20. B. Ramakrishna Rau, Michael S. Schlansker
    Embedded Computer Architecture and Automation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:75-83 [Journal]
  21. Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson
    Compilers for Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:63-69 [Journal]
  22. Michael S. Schlansker, B. Ramakrishna Rau
    EPIC: Explicititly Parallel Instruction Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:2, pp:37-45 [Journal]
  23. Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
    Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1355-1371 [Journal]
  24. Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:4, pp:376-408 [Journal]

  25. Systematically derived instruction sets for high-level language support. [Citation Graph (, )][DBLP]


  26. High-performance ethernet-based communications for future multi-core processors. [Citation Graph (, )][DBLP]


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