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Luiz André Barroso:
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Publications of Author
- Parthasarathy Ranganathan, Kourosh Gharachorloo, Sarita V. Adve, Luiz André Barroso
Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors. [Citation Graph (1, 0)][DBLP] ASPLOS, 1998, pp:307-318 [Conf]
- Luiz André Barroso, Kourosh Gharachorloo, Edouard Bugnion
Memory System Characterization of Commercial Workloads. [Citation Graph (1, 0)][DBLP] ISCA, 1998, pp:3-14 [Conf]
- Jack L. Lo, Luiz André Barroso, Susan J. Eggers, Kourosh Gharachorloo, Henry M. Levy, Sujay S. Parekh
An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. [Citation Graph (1, 0)][DBLP] ISCA, 1998, pp:39-50 [Conf]
- Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois
The Design of RPM: An FPGA-based Multiprocessor Emulator. [Citation Graph (0, 0)][DBLP] FPGA, 1995, pp:60-66 [Conf]
- Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese
Impact of Chip-Level Integration on Performance of OLTP Workloads. [Citation Graph (0, 0)][DBLP] HPCA, 2000, pp:3-14 [Conf]
- Luiz André Barroso, Michel Dubois
Cache Coherence on a Slotted Ring. [Citation Graph (0, 0)][DBLP] ICPP (1), 1991, pp:230-237 [Conf]
- Luiz André Barroso, Michel Dubois
The Performance of Cache-Coherent Ring-based Multiprocessors. [Citation Graph (0, 0)][DBLP] ISCA, 1993, pp:268-277 [Conf]
- Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese
Piranha: a scalable architecture based on single-chip multiprocessing. [Citation Graph (0, 0)][DBLP] ISCA, 2000, pp:282-293 [Conf]
- Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero
Code layout optimizations for transaction processing workloads. [Citation Graph (0, 0)][DBLP] ISCA, 2001, pp:155-164 [Conf]
- Michel Dubois, Luiz André Barroso, Yung-Syau Chen, Koray Öner
Scalability Problems in Multiprocessors with Private Caches. [Citation Graph (0, 0)][DBLP] PARLE, 1992, pp:211-230 [Conf]
- Michel Dubois, Jin-Chin Wang, Luiz André Barroso, KangWoo Lee, Yung-Syau Chen
Delayed consistency and its effects on the miss rate of parallel programs. [Citation Graph (0, 0)][DBLP] SC, 1991, pp:197-206 [Conf]
- Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Koray Öner, Michel Dubois
RPM: A Rapid Prototyping Engine for Multiprocessor Systems. [Citation Graph (0, 0)][DBLP] IEEE Computer, 1995, v:28, n:2, pp:26-34 [Journal]
- Daniel A. Menascé, Luiz André Barroso
A Methodology for Performance Evaluation of Parallel Applications on Multiprocessors. [Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 1992, v:14, n:1, pp:1-14 [Journal]
- Luiz André Barroso, Jeffrey Dean, Urs Hölzle
Web Search for a Planet: The Google Cluster Architecture. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:2, pp:22-28 [Journal]
- Luiz André Barroso
The price of performance. [Citation Graph (0, 0)][DBLP] ACM Queue, 2005, v:3, n:7, pp:48-53 [Journal]
- Luiz André Barroso, Michel Dubois
Performance Evaluation of the Slotted Ring Multiprocessor. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1995, v:44, n:7, pp:878-890 [Journal]
- Xiaobo Fan, Wolf-Dietrich Weber, Luiz André Barroso
Power provisioning for a warehouse-sized computer. [Citation Graph (0, 0)][DBLP] ISCA, 2007, pp:13-23 [Conf]
- Luiz André Barroso
Warehouse-Sized Workloads. [Citation Graph (0, 0)][DBLP] IISWC, 2006, pp:3- [Conf]
Failure Trends in a Large Disk Drive Population. [Citation Graph (, )][DBLP]
All watts considered. [Citation Graph (, )][DBLP]
Warehouse-scale Computers. [Citation Graph (, )][DBLP]
The Case for Energy-Proportional Computing. [Citation Graph (, )][DBLP]
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