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Alex Ramírez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Reducing Fetch Architecture Complexity Using Procedure Inlining. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:97-106 [Conf]
  2. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    The Effect of Code Reordering on Branch Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:189-198 [Conf]
  3. Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero
    Branch predictor guided instruction decoding. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:202-211 [Conf]
  4. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Architectural support for real-time task scheduling in SMT processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:166-176 [Conf]
  5. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Predictable performance in SMT processors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:433-443 [Conf]
  6. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Implicit vs. Explicit Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:44-51 [Conf]
  7. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Feasibility of QoS for SMT. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:535-540 [Conf]
  8. Carlos Navarro, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    On the Performance of Fetch Engines Running DSS Workloads. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:940-949 [Conf]
  9. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    Branch Prediction Using Profile Data. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:386-393 [Conf]
  10. Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero
    A Comparative Study of Redundancy in Trace Caches (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:512-516 [Conf]
  11. Ayose Falcón, Alex Ramírez, Mateo Valero
    A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:244-253 [Conf]
  12. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    Trace Cache Redundancy: Red & Blue Traces. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:325-0 [Conf]
  13. Carmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero
    A Complexity-Effective Simultaneous Multithreading Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:157-164 [Conf]
  14. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas
    Optimization of Instruction Fetch for Decision Support Workloads. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:238-245 [Conf]
  15. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero
    Software trace cache. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:119-126 [Conf]
  16. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
    DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  17. Ayose Falcón, Alex Ramírez, Mateo Valero
    Effective Instruction Prefetching via Fetch Prestaging. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  18. Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero
    Prophet/Critic Hybrid Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:250-263 [Conf]
  19. Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero
    Code layout optimizations for transaction processing workloads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:155-164 [Conf]
  20. Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero
    Improving Memory Latency Aware Fetch Policies for SMT Processors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:70-85 [Conf]
  21. Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero
    Studying New Ways for Improving Adaptive History Length Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:271-280 [Conf]
  22. Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Tolerating Branch Predictor Latency on SMT. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:86-98 [Conf]
  23. Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero
    A Comprehensive Analysis of Indirect Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:133-145 [Conf]
  24. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
    Dynamically Controlled Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:171-182 [Conf]
  25. Alex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero
    Fetching instruction streams. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:371-382 [Conf]
  26. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas
    Software Trace Cache for Commercial Applications. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2002, v:30, n:5, pp:373-395 [Journal]
  27. Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero
    Better Branch Prediction Through Prophet/Critic Hybrids. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:1, pp:80-89 [Journal]
  28. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández
    QoS for High-Performance SMT Processors in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:24-31 [Journal]
  29. Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    A low-complexity fetch architecture for high-performance superscalar processors. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:2, pp:220-245 [Journal]
  30. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Predictable Performance in SMT Processors: Synergy between the OS and SMTs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:7, pp:785-799 [Journal]
  31. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    Software Trace Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:1, pp:22-35 [Journal]
  32. Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero
    On the Problem of Minimizing Workload Execution Time in SMT Processors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:66-73 [Conf]
  33. Paul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé
    A Streaming Machine Description and Programming Model. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:107-116 [Conf]
  34. Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
    Online Prediction of Applications Cache Utility. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:169-177 [Conf]
  35. Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero
    Performance Analysis of Sequence Alignment Applications. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:51-60 [Conf]
  36. Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Enlarging Instruction Streams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1342-1357 [Journal]

  37. MLP-Aware Dynamic Cache Partitioning. [Citation Graph (, )][DBLP]


  38. Mapping stream programs onto heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]


  39. Quantitative analysis of sequence alignment applications on multiprocessor architectures. [Citation Graph (, )][DBLP]


  40. Starsscheck: A Tool to Find Errors in Task-Based Parallel Programs. [Citation Graph (, )][DBLP]


  41. Long DNA Sequence Comparison on Multicore Architectures. [Citation Graph (, )][DBLP]


  42. Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors. [Citation Graph (, )][DBLP]


  43. MLP-Aware Dynamic Cache Partitioning. [Citation Graph (, )][DBLP]


  44. Parallel H.264 Decoding on an Embedded Multicore Processor. [Citation Graph (, )][DBLP]


  45. MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. [Citation Graph (, )][DBLP]


  46. Analysis of video filtering on the cell processor. [Citation Graph (, )][DBLP]


  47. Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications. [Citation Graph (, )][DBLP]


  48. Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. [Citation Graph (, )][DBLP]


  49. On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. [Citation Graph (, )][DBLP]


  50. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. [Citation Graph (, )][DBLP]


  51. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. [Citation Graph (, )][DBLP]


  52. Thread to Core Assignment in SMT On-Chip Multiprocessors. [Citation Graph (, )][DBLP]


  53. Scalability Analysis of Progressive Alignment on a Multicore. [Citation Graph (, )][DBLP]


  54. Explaining Dynamic Cache Partitioning Speed Ups. [Citation Graph (, )][DBLP]


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