Conferences in DBLP
Christian Piguet The First Quartz Electronic Watch. [Citation Graph (0, 0)][DBLP ] Conf ] Domenik Helms , Eike Schmidt , Arne Schulz , Ansgar Stammermann , Wolfgang Nebel An Improved Power Macro-Model for Arithmetic Datapath Components. [Citation Graph (0, 0)][DBLP ] Conf ] Hoang Q. Dao , Vojin G. Oklobdzija Performance Comparison of VLSI Adders Using Logical Effort. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Pessolano , Joep L. W. Kessels , Ad M. G. Peeters MDSP: A High-Performance Low-Power DSP Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Antonio Carballo , Sani R. Nassif Impact of Technology in Power-Grid-Induced Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Windschiegl , Paul Zuber , Walter Stechele Exploiting Metal Layer Characteristics for Low-Power Routing. [Citation Graph (0, 0)][DBLP ] Conf ] F. Picot , P. Coll , Daniel Auvergne Crosstalk Measurement Technique for CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Spiridon Nikolaidis , Nikolaos Kavvadias , P. Neofotistos , K. Kosmatopoulos , T. Laopoulos , Labros Bisdounis Instrumentation Set-up for Instruction Level Power Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanuel Allier , Laurent Fesquet , Marc Renaudin , Gilles Sicard Low-Power Asynchronous A/D Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Igor Lemberski , Mark B. Josephs Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Saas , Josef A. Nossek Resonant Multistage Charging of Dominant Capacitances. [Citation Graph (0, 0)][DBLP ] Conf ] Oscar Garnica , Juan Lanchares , Román Hermida A New Methodology to Design Low-Power Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Blotti , Maurizio Castellucci , Roberto Saletti Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. [Citation Graph (0, 0)][DBLP ] Conf ] Vojin G. Oklobdzija Clocking and Clocked Storage Elements in Multi-GHz Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Torsten Mahnke , Walter Stechele , Wolfgang Hoeld Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] A. Landrault , L. Pellier , A. Richard , C. Jay , Michel Robert , Daniel Auvergne Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Soha Hassoun , Karem A. Sakallah , David Blaauw Robust SAT-Based Search Algorithm for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Kyu-won Choi , Abhijit Chatterjee PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel González , Antonio García , Graham A. Jullien , Javier Ramírez , Luis Parrilla , Antonio Lloris-Ruíz A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mario R. Casu , Mariagrazia Graziano , Guido Masera , Gianluca Piccinini , M. M. Prono , Maurizio Zamboni Clock Distribution Network Optimization under Self-Heating and Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Raúl Jiménez , Pilar Parra , Pedro Sanmartín , Antonio J. Acosta A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Rosselló , Jaume Segura A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Spiridon Nikolaidis , H. Pournara , Alexander Chatzigeorgiou Output Waveform Evaluation of Basic Pass Transistor Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Alioto , Gaetano Palumbo , Massimo Poli An Approach to Energy Consumption Modeling in RC Ladder Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Maurine , Nadine Azémard , Daniel Auvergne Structure Independent Representation of Output Transition Time for CMOS Library. [Citation Graph (0, 0)][DBLP ] Conf ] Murali Jayapala , Francisco Barat , Pieter Op de Beeck , Francky Catthoor , Geert Deconinck , Henk Corporaal A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Xuemei Zhao , Yizheng Ye Design and Realization of a Low Power Register File Using Energy Model. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takamura , Koji Inoue , Vasily G. Moshnyaga Register File Energy Reduction by Operand Data Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitry Ponomarev , Gurhan Kucuk , Kanad Ghose Energy-Efficient Design of the Reorder Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoo Itoh Trends in Ultralow-Voltage RAM Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Enrico Macii Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos D. Zervas , G. Pagkless , Minas Dasygenis , Dimitrios Soudris Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Senn , Nathalie Julien , Johann Laurent , Eric Martin Power Consumption Estimation of a C Program for Data-Intensive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Claudia Kretzschmar , Robert Siegmund , Dietmar Müller A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission. [Citation Graph (0, 0)][DBLP ] Conf ] C. Baena , Jorge Juan-Chico , Manuel J. Bellido , Paulino Ruiz-de-Clavijo , C. J. Jiménez , Manuel Valencia Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo Sutter , Elias Todorovich , Sergio López-Buedo , Eduardo I. Boemo Low-Power FSMs in FPGA: Encoding Alternatives. [Citation Graph (0, 0)][DBLP ] Conf ] Alejandro Linares-Barranco , Gabriel Jiménez , Antón Civit , Bernabé Linares-Barranco Synthetic Generation of Events for Address-Event-Representation Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Sato , Itsujiro Arita Reducing Energy Consumption via Low-Cost Value Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed Es Salhiene , Laurent Fesquet , Marc Renaudin Dynamic Voltage Scheduling for Real Time Asynchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Paulino Ruiz-de-Clavijo , Jorge Juan-Chico , Manuel J. Bellido , Alejandro Millán , David Guerrero Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. [Citation Graph (0, 0)][DBLP ] Conf ] Kostas Masselos , Panagiotis Merakos , Constantinos E. Goutis Power Efficient Vector Quantization Design Using Pixel Truncation. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Wróblewski , Florian Auernhammer , Josef A. Nossek Minimizing Spurious Switching Activities in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Alioto , Gaetano Palumbo Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Gregorio Cappuccino , Giuseppe Cocorullo Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. [Citation Graph (0, 0)][DBLP ] Conf ] Pilar Parra , Antonio J. Acosta , Manuel Valencia Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. [Citation Graph (0, 0)][DBLP ] Conf ] Achim Freimann Probabilistic Power Estimation for Digital Signal Processing Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Rosario Mita , Gaetano Palumbo Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. [Citation Graph (0, 0)][DBLP ] Conf ] Alejandro Millán , Jorge Juan-Chico , Manuel J. Bellido , Paulino Ruiz-de-Clavijo , David Guerrero Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). [Citation Graph (0, 0)][DBLP ] Conf ] Razvan Ionita , Andrei Vladimirescu , Paul G. A. Jespers Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems. [Citation Graph (0, 0)][DBLP ] Conf ] 