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Hideo Ito :
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Abderrahim Doumar , Hideo Ito Testing approach within FPGA-based fault tolerant systems. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:411-416 [Conf ] Abderrahim Doumar , Hideo Ito Testing the Logic Cells and Interconnect Resources for FPGAs. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1999, pp:369-374 [Conf ] Lihong Tong , Kazuki Suzuki , Hideo Ito Optimal Seed Generation for Delay Fault Detection BIST. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2002, pp:116-121 [Conf ] Gang Zeng , Hideo Ito Concurrent core test for SOC using shared test set and scan chain disable. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:1045-1050 [Conf ] Hideo Ito , Takashi Yagi Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. [Citation Graph (0, 0)][DBLP ] DFT, 1994, pp:177-184 [Conf ] Hideo Ito A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. [Citation Graph (0, 0)][DBLP ] DFT, 1993, pp:80-87 [Conf ] Abderrahim Doumar , Hideo Ito Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. [Citation Graph (0, 0)][DBLP ] DFT, 2000, pp:134-142 [Conf ] Abderrahim Doumar , Satoshi Kaneko , Hideo Ito Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. [Citation Graph (0, 0)][DBLP ] DFT, 1999, pp:377-385 [Conf ] Gang Zeng , Hideo Ito Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:503-510 [Conf ] Gang Zeng , Hideo Ito Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:413-421 [Conf ] Yoichi Sasaki , Kazuteru Namba , Hideo Ito Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. [Citation Graph (0, 0)][DBLP ] DFT, 2006, pp:327-335 [Conf ] Gang Zeng , Youhua Shi , Toshinori Takabatake , Masao Yanagisawa , Hideo Ito Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. [Citation Graph (0, 0)][DBLP ] DFT, 2006, pp:136-144 [Conf ] Gang Zeng , Hideo Ito Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:143-146 [Conf ] Kentaroh Katoh , Abderrahim Doumar , Hideo Ito Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. [Citation Graph (0, 0)][DBLP ] IOLTS, 2005, pp:203-204 [Conf ] Keiichi Kaneko , Hideo Ito Fault-Tolerant Routing Algorithms for Hypercube Networks. [Citation Graph (0, 0)][DBLP ] IPPS/SPDP, 1999, pp:218-224 [Conf ] Toshinori Takabatake , Keiichi Kaneko , Hideo Ito Generalized Hierarchical Completely-Connected Networks. [Citation Graph (0, 0)][DBLP ] ISPAN, 1999, pp:68-73 [Conf ] Toshinori Takabatake , Masato Kitakami , Hideo Ito A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. [Citation Graph (0, 0)][DBLP ] IASTED PDCS, 2002, pp:619-624 [Conf ] Manabu Sueishi , Masato Kitakami , Hideo Ito Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. [Citation Graph (0, 0)][DBLP ] PRDC, 2004, pp:183-190 [Conf ] Masato Kitakami , Shunji Kubota , Hideo Ito Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. [Citation Graph (0, 0)][DBLP ] PRDC, 2001, pp:319-324 [Conf ] Toshinori Takabatake , Masato Kitakami , Hideo Ito Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. [Citation Graph (0, 0)][DBLP ] PRDC, 2001, pp:127-136 [Conf ] Toshinori Takabatake , Masato Kitakami , Hideo Ito Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. [Citation Graph (0, 0)][DBLP ] PRDC, 2002, pp:137-144 [Conf ] Kazuteru Namba , Hideo Ito Design of Defect Tolerant Wallace Multiplier. [Citation Graph (0, 0)][DBLP ] PRDC, 2005, pp:300-304 [Conf ] Gang Zeng , Hideo Ito Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. [Citation Graph (0, 0)][DBLP ] VTS, 2004, pp:355-360 [Conf ] Kentaroh Katoh , Hideo Ito Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] European Test Symposium, 2006, pp:69-74 [Conf ] Abderrahim Doumar , Hideo Ito Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:386-405 [Journal ] A Delay Measurement Technique Using Signature Registers. [Citation Graph (, )][DBLP ] Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. [Citation Graph (, )][DBLP ] Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. [Citation Graph (, )][DBLP ] Testing of Switch Blocks in Three-Dimensional FPGA. [Citation Graph (, )][DBLP ] Soft Error Hardened FF Capable of Detecting Wide Error Pulse. [Citation Graph (, )][DBLP ] Delay Fault Testability on Two-Rail Logic Circuits. [Citation Graph (, )][DBLP ] Dependability Evaluation for Internet-Based Remote Systems. [Citation Graph (, )][DBLP ] An Automatic Testing and Diagnosis for FPGAs. [Citation Graph (, )][DBLP ] LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. [Citation Graph (, )][DBLP ] Path Delay Fault Test Set for Two-Rail Logic Circuits. [Citation Graph (, )][DBLP ] Search in 0.035secs, Finished in 0.036secs