Search the dblp DataBase

Publications of Author

1. Abderrahim Doumar, Hideo Ito
   Testing approach within FPGA-based fault tolerant systems. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:411-416 [Conf]
   
2. Abderrahim Doumar, Hideo Ito
   Testing the Logic Cells and Interconnect Resources for FPGAs. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1999, pp:369-374 [Conf]
   
3. Lihong Tong, Kazuki Suzuki, Hideo Ito
   Optimal Seed Generation for Delay Fault Detection BIST. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2002, pp:116-121 [Conf]
   
4. Gang Zeng, Hideo Ito
   Concurrent core test for SOC using shared test set and scan chain disable. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:1045-1050 [Conf]
   
5. Hideo Ito, Takashi Yagi
   Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:177-184 [Conf]
   
6. Hideo Ito
   A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. [Citation Graph (0, 0)][DBLP]
   DFT, 1993, pp:80-87 [Conf]
   
7. Abderrahim Doumar, Hideo Ito
   Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. [Citation Graph (0, 0)][DBLP]
   DFT, 2000, pp:134-142 [Conf]
   
8. Abderrahim Doumar, Satoshi Kaneko, Hideo Ito
   Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. [Citation Graph (0, 0)][DBLP]
   DFT, 1999, pp:377-385 [Conf]
   
9. Gang Zeng, Hideo Ito
   Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. [Citation Graph (0, 0)][DBLP]
   DFT, 2003, pp:503-510 [Conf]
   
10. Gang Zeng, Hideo Ito
    Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:413-421 [Conf]
    
11. Yoichi Sasaki, Kazuteru Namba, Hideo Ito
    Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:327-335 [Conf]
    
12. Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito
    Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:136-144 [Conf]
    
13. Gang Zeng, Hideo Ito
    Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:143-146 [Conf]
    
14. Kentaroh Katoh, Abderrahim Doumar, Hideo Ito
    Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:203-204 [Conf]
    
15. Keiichi Kaneko, Hideo Ito
    Fault-Tolerant Routing Algorithms for Hypercube Networks. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:218-224 [Conf]
    
16. Toshinori Takabatake, Keiichi Kaneko, Hideo Ito
    Generalized Hierarchical Completely-Connected Networks. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:68-73 [Conf]
    
17. Toshinori Takabatake, Masato Kitakami, Hideo Ito
    A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:619-624 [Conf]
    
18. Manabu Sueishi, Masato Kitakami, Hideo Ito
    Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. [Citation Graph (0, 0)][DBLP]
    PRDC, 2004, pp:183-190 [Conf]
    
19. Masato Kitakami, Shunji Kubota, Hideo Ito
    Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:319-324 [Conf]
    
20. Toshinori Takabatake, Masato Kitakami, Hideo Ito
    Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:127-136 [Conf]
    
21. Toshinori Takabatake, Masato Kitakami, Hideo Ito
    Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:137-144 [Conf]
    
22. Kazuteru Namba, Hideo Ito
    Design of Defect Tolerant Wallace Multiplier. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:300-304 [Conf]
    
23. Gang Zeng, Hideo Ito
    Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:355-360 [Conf]
    
24. Kentaroh Katoh, Hideo Ito
    Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:69-74 [Conf]
    
25. Abderrahim Doumar, Hideo Ito
    Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:386-405 [Journal]
    
26. 
    A Delay Measurement Technique Using Signature Registers. [Citation Graph (, )][DBLP]
    
    
27. 
    Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. [Citation Graph (, )][DBLP]
    
    
28. 
    Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. [Citation Graph (, )][DBLP]
    
    
29. 
    Testing of Switch Blocks in Three-Dimensional FPGA. [Citation Graph (, )][DBLP]
    
    
30. 
    Soft Error Hardened FF Capable of Detecting Wide Error Pulse. [Citation Graph (, )][DBLP]
    
    
31. 
    Delay Fault Testability on Two-Rail Logic Circuits. [Citation Graph (, )][DBLP]
    
    
32. 
    Dependability Evaluation for Internet-Based Remote Systems. [Citation Graph (, )][DBLP]
    
    
33. 
    An Automatic Testing and Diagnosis for FPGAs. [Citation Graph (, )][DBLP]
    
    
34. 
    LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. [Citation Graph (, )][DBLP]
    
    
35. 
    Path Delay Fault Test Set for Two-Rail Logic Circuits. [Citation Graph (, )][DBLP]