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Bruce R. Childers: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bruce R. Childers, Jack W. Davidson
    Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:57-70 [Conf]
  2. Naveen Kumar, Bruce R. Childers, Mary Lou Soffa
    Tdb: a source-level debugger for dynamically translated programs. [Citation Graph (0, 0)][DBLP]
    AADEBUG, 2005, pp:123-132 [Conf]
  3. Bruce R. Childers, Jack W. Davidson
    Architectural Considerations for Application-Specific Counterflow Pipelines. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:3-22 [Conf]
  4. Jonathan Misurda, James A. Clause, Juliya L. Reed, Bruce R. Childers, Mary Lou Soffa
    Jazz: A Tool for Demand-Driven Structural Testing. [Citation Graph (0, 0)][DBLP]
    CC, 2005, pp:242-245 [Conf]
  5. Jason Hiser, Daniel Williams, Wei Hu, Jack W. Davidson, Jason Mars, Bruce R. Childers
    Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:61-73 [Conf]
  6. Min Zhao, Bruce R. Childers, Mary Lou Soffa
    Model-Based Framework: An Approach for Profit-Driven Optimization. [Citation Graph (0, 0)][DBLP]
    CGO, 2005, pp:317-327 [Conf]
  7. Kevin Scott, Naveen Kumar, S. Velusamy, Bruce R. Childers, Jack W. Davidson, Mary Lou Soffa
    Retargetable and Reconfigurable Software Dynamic Translation. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:36-47 [Conf]
  8. Daniel Mossé, Nevine AbouGhazaleh, Bruce R. Childers, Rami G. Melhem
    Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM. [Citation Graph (0, 0)][DBLP]
    Power-aware Computing Systems, 2005, pp:- [Conf]
  9. Stacey Shogan, Bruce R. Childers
    Compact Binaries with Code Compression in a Software Dynamic Translator. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1052-1059 [Conf]
  10. Shukang Zhou, Bruce R. Childers, Naveen Kumar
    Profile Guided Management of Code Partitions for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1396-1399 [Conf]
  11. Bruce R. Childers, Jack W. Davidson
    An Infrastructure for Designing Custom Embedded Counter-flow Pipelines. [Citation Graph (0, 0)][DBLP]
    HICSS, 2000, pp:- [Conf]
  12. Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem
    Near-memory Caching for Improved Energy Consumption. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:105-110 [Conf]
  13. Jonathan Misurda, James A. Clause, Juliya L. Reed, Bruce R. Childers, Mary Lou Soffa
    Demand-driven structural testing with dynamic instrumentation. [Citation Graph (0, 0)][DBLP]
    ICSE, 2005, pp:156-165 [Conf]
  14. Bruce R. Childers, Jack W. Davidson, Mary Lou Soffa
    Continuous Compilation: A New Approach to Aggressive and Adaptive Code Transformation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:205- [Conf]
  15. Kevin Scott, Naveen Kumar, Bruce R. Childers, Jack W. Davidson, Mary Lou Soffa
    Overhead Reduction Techniques for Software Dynamic Translation. [Citation Graph (0, 0)][DBLP]
    IPDPS Next Generation Software Program - NSFNGS - PI Workshop, 2004, pp:- [Conf]
  16. Jason Hiser, Naveen Kumar, Min Zhao, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Mary Lou Soffa
    Techniques and tools for dynamic optimization. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  17. Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
    Performance of Graceful Degradation for Cache Faults. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:409-415 [Conf]
  18. Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem, Matthew Craven
    Energy management for real-time embedded applications with compiler support. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:284-293 [Conf]
  19. Bruce R. Childers, Jack W. Davidson
    A Design Environment for Counterflow Pipeline Synthesis. [Citation Graph (0, 0)][DBLP]
    LCTES, 1998, pp:113-234 [Conf]
  20. Bruce R. Childers, Tarun Nakra
    Reordering Memory Bus Transactions for Reduced Power Consumption. [Citation Graph (0, 0)][DBLP]
    LCTES, 2000, pp:146-161 [Conf]
  21. Min Zhao, Bruce R. Childers, Mary Lou Soffa
    Predicting the impact of optimizations for embedded systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:1-11 [Conf]
  22. Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis
    Short Courses in System-on-a-Chip (SoC) Design. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:126-127 [Conf]
  23. Bruce R. Childers, Mary Lou Soffa, J. Beaver, L. Ber, K. Cammarata, T. Kane, J. Litman, Jonathan Misurda
    SoftTest: a framework for software testing of Java programs. [Citation Graph (0, 0)][DBLP]
    OOPSLA Workshop on Eclipse Technology eXchange, 2003, pp:79-83 [Conf]
  24. Naveen Kumar, Bruce R. Childers, Mary Lou Soffa
    Low overhead program monitoring and profiling. [Citation Graph (0, 0)][DBLP]
    PASTE, 2005, pp:28-34 [Conf]
  25. Nevine AbouGhazaleh, Daniel Mossé, Bruce R. Childers, Rami G. Melhem, Matthew Craven
    Collaborative Operating System and Compiler Power Management for Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2003, pp:133-0 [Conf]
  26. Dakai Zhu, Rami G. Melhem, Bruce R. Childers
    Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multi-Processor Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 2001, pp:84-94 [Conf]
  27. Yuqiang Huang, Bruce R. Childers, Mary Lou Soffa
    Catching and Identifying Bugs in Register Allocation. [Citation Graph (0, 0)][DBLP]
    SAS, 2006, pp:281-300 [Conf]
  28. Maurício L. Pilla, Philippe Olivier Alexandre Navaux, Bruce R. Childers, Amarildo T. da Costa, Felipe Maia Galvão França
    Value Predictors for Reuse through Speculation on Traces. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:48-55 [Conf]
  29. Maurício L. Pilla, Amarildo T. da Costa, Felipe M. G. França, Bruce R. Childers, Mary Lou Soffa
    The Limits of Speculative Trace Reuse on Deeply Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:36-45 [Conf]
  30. Naveen Kumar, Jonathan Misurda, Bruce R. Childers, Mary Lou Soffa
    Instrumentation in software dynamic translators for self-managed systems. [Citation Graph (0, 0)][DBLP]
    WOSS, 2004, pp:90-94 [Conf]
  31. Shukang Zhou, Bruce R. Childers, Mary Lou Soffa
    Planning for code buffer management in distributed virtual execution environments. [Citation Graph (0, 0)][DBLP]
    VEE, 2005, pp:100-109 [Conf]
  32. Jason Hiser, Daniel Williams, Adrian Filipi, Jack W. Davidson, Bruce R. Childers
    Evaluating fragment construction policies for SDT systems. [Citation Graph (0, 0)][DBLP]
    VEE, 2006, pp:122-132 [Conf]
  33. Bruce R. Childers, James P. Cohoon, Jack W. Davidson, Peter Valle
    The Design of EzWindows: A Graphics API for an Introductory Programming Course [Citation Graph (0, 0)][DBLP]
    CoRR, 1998, v:0, n:, pp:- [Journal]
  34. Naveen Kumar, Bruce R. Childers, Daniel Williams, Jack W. Davidson, Mary Lou Soffa
    Compile-Time Planning for Overhead Reduction in Software Dynamic Translators. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:2-3, pp:103-114 [Journal]
  35. Min Zhao, Bruce R. Childers, Mary Lou Soffa
    An approach toward profit-driven optimization. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:3, pp:231-262 [Journal]
  36. Bruce R. Childers, Jack W. Davidson
    Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:2, pp:141-158 [Journal]
  37. Ali R. Hurson, Bruce R. Childers
    Message from the Guest Editors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:8, pp:767-768 [Journal]
  38. Nevine AbouGhazaleh, Daniel Mossé, Bruce R. Childers, Rami G. Melhem
    Collaborative operating system and compiler power management for real-time applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:82-115 [Journal]
  39. Dakai Zhu, Rami G. Melhem, Bruce R. Childers
    Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multiprocessor Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:7, pp:686-700 [Journal]
  40. Bruce R. Childers, Jack W. Davidson
    An infrastructure for designing custom embedded wide counterflow pipelines. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:1, pp:27-40 [Journal]
  41. Jose Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser, Jonathan Misurda
    Fragment cache management for dynamic binary translators in embedded systems with scratchpad. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:75-84 [Conf]
  42. Apala Guha, Jason Hiser, Naveen Kumar, Jing Yang, Min Zhao, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Kim M. Hazelwood, Mary Lou Soffa
    Virtual Execution Environments: Support and Tools. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  43. Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Rusu, Ruibin Xu, Frank Liberato, Bruce R. Childers, Daniel Mossé, Rami G. Melhem
    Integrated CPU and l2 cache voltage scaling using machine learning. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:41-50 [Conf]
  44. Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem
    Near-Memory Caching for Improved Energy Consumption. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:11, pp:1441-1455 [Journal]

  45. Reducing pressure in bounded DBT code caches. [Citation Graph (, )][DBLP]


  46. A Framework for Exploring Optimization Properties. [Citation Graph (, )][DBLP]


  47. Transparent Debugging of Dynamically Optimized Code. [Citation Graph (, )][DBLP]


  48. Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators. [Citation Graph (, )][DBLP]


  49. Increasing PCM main memory lifetime. [Citation Graph (, )][DBLP]


  50. Integrated CPU Cache Power Management in Multiple Clock Domain Processors. [Citation Graph (, )][DBLP]


  51. Network I/O Extensibility without Administrator Privilege. [Citation Graph (, )][DBLP]


  52. Exploring the interplay of yield, area, and performance in processor caches. [Citation Graph (, )][DBLP]


  53. Addressing the challenges of DBT for the ARM architecture. [Citation Graph (, )][DBLP]


  54. Using PCM in Next-generation Embedded Space Applications. [Citation Graph (, )][DBLP]


  55. A Speculative Trace Reuse Architecture with Reduced Hardware Requirements. [Citation Graph (, )][DBLP]


  56. Running a Java VM inside an operating system kernel. [Citation Graph (, )][DBLP]


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