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Publications of Author

1. Partha Biswas, Nikil D. Dutt
   Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. [Citation Graph (0, 0)][DBLP]
   CASES, 2003, pp:104-112 [Conf]
   
2. Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt
   Introduction of local memory elements in instruction set extensions. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:729-734 [Conf]
   
3. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
   ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:1246-1251 [Conf]
   
4. Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
   Automatic identification of application-specific functional units with architecturally visible storage. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:212-217 [Conf]
   
5. Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau
   An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:402-408 [Conf]
   
6. Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi
   A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . [Citation Graph (0, 0)][DBLP]
   ISSS, 2002, pp:120-125 [Conf]
   
7. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
   Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:651-656 [Conf]
   
8. Partha Biswas, Nikil D. Dutt
   Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:10, pp:1216-1226 [Journal]
   
9. Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau
   Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:123-146 [Journal]
   
10. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:754-762 [Journal]
    
11. Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
12. 
    Comprehensive isomorphic subtree enumeration. [Citation Graph (, )][DBLP]