Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1997, volume: 16, number: 9

1. Christoph Wasshuber, Hans Kosina, Siegfried Selberherr
   SIMON-A simulator for single-electron tunnel devices and circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:937-944 [Journal]
   
2. Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm
   Optimal algorithms for recovery point insertion in recoverable microarchitectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:945-955 [Journal]
   
3. Scott Hauck, Gaetano Borriello
   Pin assignment for multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:956-964 [Journal]
   
4. Ashok Vittal, Malgorzata Marek-Sadowska
   Low-power buffered clock tree design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:965-975 [Journal]
   
5. Hannah Honghua Yang, Martin D. F. Wong
   Circuit clustering for delay minimization under area and pin constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:976-986 [Journal]
   
6. Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb
   New fault models and efficient BIST algorithms for dual-port memories. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:987-1000 [Journal]
   
7. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
   Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1001-1014 [Journal]
   
8. Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo
   Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1015-1024 [Journal]
   
9. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
   Identifying invalid states for sequential circuit test generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1025-1033 [Journal]
   
10. Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
    A genetic algorithm framework for test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1034-1044 [Journal]
    
11. Xiaoling Sun, Micaela Serra
    On-line and off-line testing with shared resources: a new BIST approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1045-1056 [Journal]