Journals in DBLP

IEEE Trans. VLSI Syst.
2006, volume: 14, number: 4

1. Byung-Do Yang, Lee-Sup Kim
   A low-power ROM using single charge-sharing capacitor and hierarchical bit line. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:313-322 [Journal]
   
2. Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi
   Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:323-335 [Journal]
   
3. Byonghyo Shim, Naresh R. Shanbhag
   Energy-efficient soft error-tolerant digital signal processing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:336-348 [Journal]
   
4. Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya
   Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:349-360 [Journal]
   
5. Shih-Chang Hsia, Ming-Huei Chen, Po-Shien Tsai
   VLSI implementation of low-power high-quality color interpolation processor for CCD camera. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:361-369 [Journal]
   
6. Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
   Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:370-379 [Journal]
   
7. Sangjin Hong, Kyoung-Su Park, Jun-Hee Mun
   Design and implementation of a high-speed matrix multiplier based on word-width decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:380-392 [Journal]
   
8. Kamran Farzan, David A. Johns
   Coding schemes for chip-to-chip interconnect applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:393-406 [Journal]
   
9. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
   Linear-programming-based techniques for synthesis of network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:407-420 [Journal]
   
10. Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn
    Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:421-425 [Journal]
    
11. Chien-Ching Lin, Y.-H. Shih, Hsie-Chia Chang, Chen-Yi Lee
    A low power turbo/Viterbi decoder for 3GPP2 applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:426-430 [Journal]
    
12. Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai
    Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:430-435 [Journal]