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Bashir M. Al-Hashimi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy
    Cache size selection for performance, energy and reliability of time-constrained systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:923-928 [Conf]
  2. Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz
    Improving routing efficiency for network-on-chip through contention-aware input selection. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:36-41 [Conf]
  3. Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Symbolic model checking of Dual Transition Petri Nets. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:43-48 [Conf]
  4. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:518-525 [Conf]
  5. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:514-519 [Conf]
  6. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Minimizing test power in SRAM through reduction of pre-charge activity. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1159-1164 [Conf]
  7. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:604-611 [Conf]
  8. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Test Data Compression: The System Integrator's Perspective. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10726-10731 [Conf]
  9. Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger
    Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1372-1373 [Conf]
  10. Nicola Nicolici, Bashir M. Al-Hashimi
    Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:715-722 [Conf]
  11. Nicola Nicolici, Bashir M. Al-Hashimi
    Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:802- [Conf]
  12. Nicola Nicolici, Bashir M. Al-Hashimi
    Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:289-0 [Conf]
  13. Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi
    Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10596-10601 [Conf]
  14. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Rapid Generation of Thermal-Safe Test Schedules. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:840-845 [Conf]
  15. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:514-521 [Conf]
  16. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10960-10965 [Conf]
  17. Mauricio Varea, Bashir M. Al-Hashimi
    Dual transitions petri net based modelling technique for embedded systems specification. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:566-571 [Conf]
  18. Dong Wu, Bashir M. Al-Hashimi, Petru Eles
    Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10090-10095 [Conf]
  19. Luigi Dilillo, Bashir M. Al-Hashimi
    March CRF: an Efficient Test for Complex Read Faults in SRAM Memories. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:173-178 [Conf]
  20. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Scan Architecture for Shift and Capture Cycle Power Reduction. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:129-137 [Conf]
  21. Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:544-551 [Conf]
  22. Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:477-485 [Conf]
  23. Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles
    Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:34-41 [Conf]
  24. P. Kollig, Bashir M. Al-Hashimi
    Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:227-234 [Conf]
  25. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:362-369 [Conf]
  26. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:474-479 [Conf]
  27. Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi
    Battery-aware dynamic voltage scaling in multiprocessor embedded system. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:616-619 [Conf]
  28. Chun-Ming Chang, Bashir M. Al-Hashimi
    Analytical synthesis of voltage mode OTA-C all-pass filters for high frequency operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:461-464 [Conf]
  29. Mehdi Jafaripanah, Bashir M. Al-Hashimi, Neil M. White
    Load cell response correction using analog adaptive techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:752-755 [Conf]
  30. Mehdi Jafaripanah, Bashir M. Al-Hashimi, Neil M. White
    Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications]. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5389-5392 [Conf]
  31. Reuben Wilcock, Bashir M. Al-Hashimi
    Power-conscious design methodology for class-A switched-current wave filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:225-228 [Conf]
  32. Peter Wilson, Reuben Wilcock, Bashir M. Al-Hashimi
    A novel switched-current phase locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2815-2818 [Conf]
  33. Yan Xie, Bashir M. Al-Hashimi
    Analogue adaptive filters using wave synthesis technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:849-852 [Conf]
  34. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power constrained test scheduling using power profile manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:251-254 [Conf]
  35. J. Living, Bashir M. Al-Hashimi
    Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:478-481 [Conf]
  36. F. Dudek, Bashir M. Al-Hashimi, M. Moniri
    Compensation of nonideal effects in video-frequency sinc(x)-equalizers using tunable gm-C structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:148-151 [Conf]
  37. J. Living, Bashir M. Al-Hashimi
    New differential coefficient coding algorithm for recursive FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:379-382 [Conf]
  38. Reuben Wilcock, Bashir M. Al-Hashimi
    Application of group delay equalisation in testing fully-balanced OTA-C filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:643-646 [Conf]
  39. Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger
    Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:281-286 [Conf]
  40. Yuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi
    Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:368-373 [Conf]
  41. Marcus T. Schmitz, Bashir M. Al-Hashimi
    Considering power variations of DVS processing elements for energy minimisation in distributed systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:250-255 [Conf]
  42. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:64-73 [Conf]
  43. Nicola Nicolici, Bashir M. Al-Hashimi
    Power conscious test synthesis and scheduling for BIST RTL data paths. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:662-671 [Conf]
  44. Nicola Nicolici, Bashir M. Al-Hashimi
    Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:72-81 [Conf]
  45. Geoff Merrett, Bashir M. Al-Hashimi
    Leakage Power Analysis and Comparison of Deep Submicron Logic Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:198-207 [Conf]
  46. Simon Ogg, Bashir M. Al-Hashimi
    Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:525-529 [Conf]
  47. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:423-432 [Conf]
  48. Nicola Nicolici, Bashir M. Al-Hashimi
    Power-Conscious Test Synthesis and Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:48-55 [Journal]
  49. Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:262-265 [Journal]
  50. Nicola Nicolici, Bashir M. Al-Hashimi
    Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:6, pp:721-734 [Journal]
  51. Nicola Nicolici, Bashir M. Al-Hashimi
    Correction to the Proof of Theorem 2 in ``Parallel Signature Analysis Design with Bounds on Aliasing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1426- [Journal]
  52. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Variable-length input Huffman coding for system-on-a-chip test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:783-796 [Journal]
  53. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Addressing useless test data in core-based system-on-a-chip test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1568-1580 [Journal]
  54. Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams
    BIST hardware synthesis for RTL data paths based on testcompatibility classes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1375-1385 [Journal]
  55. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2502-2512 [Journal]
  56. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power profile manipulation: a new approach for reducing test application time under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1217-1225 [Journal]
  57. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1142-1153 [Journal]
  58. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:153-169 [Journal]
  59. Mauricio Varea, Bashir M. Al-Hashimi, Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Dual Flow Nets: Modeling the control/data-flow relation in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:54-81 [Journal]
  60. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Iterative schedule optimization for voltage scalable distributed embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:182-217 [Journal]
  61. Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi
    Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:323-335 [Journal]
  62. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Synchronization overhead in SOC compressed test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:140-152 [Journal]
  63. Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi
    Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1647-1652 [Conf]
  64. Haider Ali, Bashir M. Al-Hashimi
    Architecture Level Power-Performance Tradeoffs for Pipelined Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1791-1794 [Conf]
  65. Matthew Collins, Bashir M. Al-Hashimi
    On-Chip Time Measurement Architecture with Femtosecond Timing Resolution. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:103-110 [Conf]
  66. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
    Enhancing Delay Fault Coverage through Low Power Segmented Scan. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:21-28 [Conf]
  67. Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod
    Dynamic Voltage Scaling Aware Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:15-20 [Conf]
  68. Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini
    Reducing Interconnect Cost in NoC through Serialized Asynchronous Links. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:219- [Conf]
  69. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Rapid Generation of Thermal-Safe Test Schedules [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  70. Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy
    Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]
  71. Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi
    Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:262-275 [Journal]
  72. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Reducing Power Dissipation in SRAM during Test. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:271-280 [Journal]
  73. Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh
    New JETTA Editors, 2006. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:9-10 [Journal]

  74. Transistor-level based defect tolerance for reliable nanoelectronics. [Citation Graph (, )][DBLP]


  75. Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection. [Citation Graph (, )][DBLP]


  76. Asynchronous transient resilient links for NoC. [Citation Graph (, )][DBLP]


  77. A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems. [Citation Graph (, )][DBLP]


  78. Serialized Asynchronous Links for NoC. [Citation Graph (, )][DBLP]


  79. Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density. [Citation Graph (, )][DBLP]


  80. Integrated approach to energy harvester mixed technology modelling and performance optimisation. [Citation Graph (, )][DBLP]


  81. Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing. [Citation Graph (, )][DBLP]


  82. Selective state retention design using symbolic simulation. [Citation Graph (, )][DBLP]


  83. Variation resilient adaptive controller for subthreshold circuits. [Citation Graph (, )][DBLP]


  84. An automated design flow for vibration-based energy harvester systems. [Citation Graph (, )][DBLP]


  85. Scan based methodology for reliable state retention power gating designs. [Citation Graph (, )][DBLP]


  86. Evaluation and design exploration of solar harvested-energy prediction algorithm. [Citation Graph (, )][DBLP]


  87. Soft error-aware design optimization of low power and time-constrained embedded systems. [Citation Graph (, )][DBLP]


  88. MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC. [Citation Graph (, )][DBLP]


  89. A Structured Hardware/Software Architecture for Embedded Sensor Nodes. [Citation Graph (, )][DBLP]


  90. An Empirical Energy Model for Supercapacitor Powered Wireless Sensor Nodes. [Citation Graph (, )][DBLP]


  91. Iterative Decoding for Redistributing Energy Consumption in Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  92. A New Approach for Transient Fault Injection Using Symbolic Simulation. [Citation Graph (, )][DBLP]


  93. SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation. [Citation Graph (, )][DBLP]


  94. Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis. [Citation Graph (, )][DBLP]


  95. Reduced Z-datapath Cordic Rotator. [Citation Graph (, )][DBLP]


  96. Subthreshold FIR Filter Architecture for Ultra Low Power Applications. [Citation Graph (, )][DBLP]


  97. Design of a low power MPEG-1 motion vector reconstructor. [Citation Graph (, )][DBLP]


  98. SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks. [Citation Graph (, )][DBLP]


  99. VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation. [Citation Graph (, )][DBLP]


  100. Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry. [Citation Graph (, )][DBLP]


  101. Hardware Dependability in the Presence of Soft Errors. [Citation Graph (, )][DBLP]


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