Journals in DBLP

J. Low Power Electronics
2005, volume: 1, number: 2

1. Roozbeh Jafari, Foad Dabiri, Majid Sarrafzadeh
   Epsilon-Optimal Minimal-Skew Battery Lifetime Routing in Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:97-107 [Journal]
   
2. Arindam Mallik, Gokhan Memik
   Low Power Correlating Caches for Network Processors. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:108-118 [Journal]
   
3. Julien Lamoureux, Steven J. E. Wilton
   On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:119-132 [Journal]
   
4. Chang Woo Kang, Massoud Pedram
   A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:133-144 [Journal]
   
5. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
   Pseudo Dual Supply Voltage Domino Logic Design. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:145-152 [Journal]
   
6. Olivier Mazouffre, Hervé Lapuyade, Jean-Baptiste Begueret, Andreia Cathelin, Didier Belot, Yann Deval
   A 1 V 270 My-W 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:153-160 [Journal]
   
7. Jingzhao Ou, Viktor K. Prasanna
   Arithmetic-Level Instruction Based Energy Estimation for FPGA based Soft Processors. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:161-171 [Journal]
   
8. Emrah Acar, Anirudh Devgan, Sani R. Nassif
   Leakage and Leakage Sensitivity Computation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:172-181 [Journal]
   
9. Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar
   Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:2, pp:182-193 [Journal]
   
10. M. M. Vaseekar Kumar, Spyros Tragoudas
    Low Power Test Generation for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:194-205 [Journal]