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Ramalingam Sridhar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paul W. Palumbo, Sargur N. Srihari, Jung Soh, Ramalingam Sridhar, Victor Demjanenko
    Postal Address Block Location in Real Time. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:7, pp:34-42 [Journal]
  2. Lushan Li, Ramalingam Sridhar, Shambhu J. Upadhyaya
    A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:545-553 [Conf]
  3. Seokjin Kim, Ramalingam Sridhar
    A local clocking approach for self-timed datapath designs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:152-0 [Conf]
  4. Seokjin Kim, Ramalingam Sridhar
    Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:122-125 [Conf]
  5. Wen-jann Yang, Ramalingam Sridhar, Victor Demjanenko
    Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:232-241 [Conf]
  6. Ram K. Krishnamurthy, Ramalingam Sridhar
    A CMOS wave-pipelined image processor for real-time morphology . [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:638-0 [Conf]
  7. Xuguang Zhang, Ramalingam Sridhar
    Synchronization of Wave-Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:164-167 [Conf]
  8. Wen-jann Yang, Ramalingam Sridhar, Paul W. Palumbo
    Multi-attribute Lexicon Generation by Hyper-linked Embedded Access Structure. [Citation Graph (0, 0)][DBLP]
    IDEAS, 1997, pp:299-308 [Conf]
  9. Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif
    SRAM Local Bit Line Access Failure Analyses. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:204-209 [Conf]
  10. Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar
    Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:617-624 [Conf]
  11. Ashok Narasimhan, Ramalingam Sridhar
    Impact of Variability on Clock Skew in H-tree Clock Networks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:458-466 [Conf]
  12. Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar
    RG-SRAM: A Low Gate Leakage Memory Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:295-296 [Conf]
  13. Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar
    A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:130-133 [Conf]
  14. Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar
    A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:634-639 [Conf]
  15. Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar
    A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:491-494 [Conf]
  16. Rajesh S. Parthasarathy, Ramalingam Sridhar
    Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:495-500 [Conf]
  17. Ramalingam Sridhar
    System-on-Chip (SoC): Clocking and Synchronization Issues. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:520-0 [Conf]
  18. Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar
    High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:569-574 [Conf]
  19. Prachee Sharma, Asheq Khan, Ashok Narasimhan, Ramalingam Sridhar, Satish K. Tripathi
    Energy Conservation in Sensor Networks through Selective Node Activation. [Citation Graph (0, 0)][DBLP]
    WOWMOM, 2006, pp:115-124 [Conf]
  20. Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:4, pp:95-97 [Journal]
  21. Ranjani Sridharan, Ramalingam Sridhar, Sumita Mishra
    A robust header compression technique for wireless Ad hoc networks. [Citation Graph (0, 0)][DBLP]
    Mobile Computing and Communications Review, 2003, v:7, n:3, pp:23-24 [Journal]
  22. Vidya Bharrgavi Balasubramanyn, Geethapriya Thamilarasu, Ramalingam Sridhar
    Security Solution For Data Integrity InWireless BioSensor Networks. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2007, pp:79- [Conf]
  23. Geethapriya Thamilarasu, Ramalingam Sridhar
    Toward Building a Multi-level Robust Intrusion Detection Architecture for Distributed Mobile Networks. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2007, pp:5- [Conf]
  24. Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar
    Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:182-193 [Journal]

  25. D-RNA: Towards a DDoS Resistant Network Architecture using Social Network Analysis. [Citation Graph (, )][DBLP]


  26. A low power and low area active clock deskewing technique for sub-90nm technologies. [Citation Graph (, )][DBLP]


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