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Publications of Author

1. Xiaoliang Bai, Sujit Dey, Janusz Rajski
   Self-test methodology for at-speed test of crosstalk in chip interconnects. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:619-624 [Conf]
   
2. Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski
   Uncertainty-aware circuit optimization. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:58-63 [Conf]
   
3. Li Chen, Xiaoliang Bai, Sujit Dey
   Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:317-320 [Conf]
   
4. Chong Zhao, Xiaoliang Bai, Sujit Dey
   A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:894-899 [Conf]
   
5. Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao
   Fault modeling and simulation for crosstalk in system-on-chip interconnects. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1999, pp:297-303 [Conf]
   
6. Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas
   Noise-Aware Driver Modeling for Nanometer Technology. [Citation Graph (0, 0)][DBLP]
   ISQED, 2003, pp:177-182 [Conf]
   
7. Xiaoliang Bai, Sujit Dey, Angela Krstic
   HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:112-121 [Conf]
   
8. R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald
   An Integrated Memory Self Test and EDA Solution. [Citation Graph (0, 0)][DBLP]
   MTDT, 2004, pp:92-95 [Conf]
   
9. Xiaoliang Bai, Sujit Dey
   High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
   VTS, 2001, pp:169-177 [Conf]
   
10. Chong Zhao, Sujit Dey, Xiaoliang Bai
    Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:362-375 [Journal]
    
11. Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas
    Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1256-1263 [Journal]
    
12. Xiaoliang Bai, Sujit Dey
    High-level crosstalk defect Simulation methodology for system-on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1355-1361 [Journal]
    
13. 
    A Modified SOFM Segmentation Method in Reverse Engineering. [Citation Graph (, )][DBLP]
    
    
14. 
    A Shape Distributions Retrieval Algorithm of 3D CAD Models Based on Normal Direction. [Citation Graph (, )][DBLP]