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Publications of Author

1. Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar
   Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:151-156 [Conf]
   
2. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
   Techniques for low power realization for FIR filters. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
3. Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar
   Optimized Code Generation of Multiplication-free Linear Transforms. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:41-46 [Conf]
   
4. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
   Synthesis of multiplier-less FIR filters with minimum number of additions. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:668-671 [Conf]
   
5. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
   A Methodology for Designing Optimal Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1991, pp:283-291 [Conf]
   
6. B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
   A new methodology for the design of low-cost fail safe circuits and networks. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1995, pp:355-358 [Conf]
   
7. Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh
   Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1998, pp:110-115 [Conf]
   
8. Mahesh Mehendale, Sunil D. Sherlekar
   Power Reduction Techniques for Portable DSP Applications. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2000, pp:3- [Conf]
   
9. Mahesh Mehendale, Sunil D. Sherlekar
   Low Power Code Generation of Multiplication-free Linear Transforms. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:42-47 [Conf]
   
10. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Low power realization of FIR filters using multirate architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:370-375 [Conf]
    
11. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:124-129 [Conf]
    
12. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:12-17 [Conf]
    
13. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Extensions to Programmable DSP architectures for Reduced Power Dissipation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:37-0 [Conf]
    
14. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
    State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:15-20 [Conf]
    
15. Sunil D. Sherlekar
    Export of VLSI Design and CAD: Present and Future. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:264- [Conf]
    
16. Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran
    A Behavioral Fault Simulator for Ideal. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:14-21 [Journal]
    
17. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
    Concurrent Error Detection Using Monitoring Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:24-32 [Journal]
    
18. Sunil D. Sherlekar, P. S. Subramanian
    Conditionally robust two-pattern tests and CMOS design for testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:3, pp:325-332 [Journal]
    
19. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Low-power realization of FIR filters on programmable DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:546-553 [Journal]